Xilinx VCU110 User Manual page 135

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# External Input User SMA Differential Clock
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# EMCCLK 90 MHz Single-Ended LVCMOS
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# SI5328
# HMC SI5328B Clock U57, SI53340 Clock Buffer U165
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# CFP4 SI5328B Clock U179, SI53340 Clock Buffer U180
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# EXAMAX and INTERLAKEN SI5328B Clock U181
# EXAMAX SI53340 Clock Buffer U184
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# INTERLAKEN SI53301 Clock Buffer U196
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VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN BA20
IOSTANDARD LVDS
PACKAGE_PIN AY27
IOSTANDARD DIFF_HSTL_I [get_ports "USER_SMA_CLOCK_P"]
PACKAGE_PIN AY28
IOSTANDARD DIFF_HSTL_I [get_ports "USER_SMA_CLOCK_N"]
PACKAGE_PIN BE20
IOSTANDARD LVCMOS18
PACKAGE_PIN R11
PACKAGE_PIN R10
PACKAGE_PIN AC11
PACKAGE_PIN AC10
PACKAGE_PIN BD17
IOSTANDARD LVDS
PACKAGE_PIN BD16
IOSTANDARD LVDS
PACKAGE_PIN V34
PACKAGE_PIN V35
PACKAGE_PIN AJ37
PACKAGE_PIN AJ36
PACKAGE_PIN AE37
PACKAGE_PIN AE36
PACKAGE_PIN AA37
PACKAGE_PIN AA36
PACKAGE_PIN W37
PACKAGE_PIN W36
PACKAGE_PIN AN37
PACKAGE_PIN AN36
PACKAGE_PIN AL37
PACKAGE_PIN AL36
PACKAGE_PIN U37
PACKAGE_PIN U36
PACKAGE_PIN R37
PACKAGE_PIN R36
PACKAGE_PIN N37
PACKAGE_PIN N36
PACKAGE_PIN L37
PACKAGE_PIN L36
PACKAGE_PIN J37
PACKAGE_PIN J36
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Appendix D: Master Constraints File Listing
[get_ports "USER_SI570_CLOCK_N"]
[get_ports "USER_SI570_CLOCK_N"]
[get_ports "USER_SMA_CLOCK_P"]
[get_ports "USER_SMA_CLOCK_N"]
[get_ports "FPGA_EMCCLK"]
[get_ports "FPGA_EMCCLK"]
[get_ports "HMC_SI5328_OUT2_BUF1_C_P"]
[get_ports "HMC_SI5328_OUT2_BUF1_C_N"]
[get_ports "HMC_SI5328_OUT2_BUF2_C_P"]
[get_ports "HMC_SI5328_OUT2_BUF2_C_N"]
[get_ports "CFP4_REC_CLOCK_C_P"]
[get_ports "CFP4_REC_CLOCK_C_P"]
[get_ports "CFP4_REC_CLOCK_C_N"]
[get_ports "CFP4_REC_CLOCK_C_N"]
[get_ports "CFP4_REC_CLOCK2_C_P"]
[get_ports "CFP4_REC_CLOCK2_C_N"]
[get_ports "CFP4_SI5328_OUT1_BUF1_C_N"]
[get_ports "CFP4_SI5328_OUT1_BUF1_C_P"]
[get_ports "CFP4_SI5328_OUT1_BUF2_C_N"]
[get_ports "CFP4_SI5328_OUT1_BUF2_C_P"]
[get_ports "CFP4_SI5328_OUT1_BUF3_C_N"]
[get_ports "CFP4_SI5328_OUT1_BUF3_C_P"]
[get_ports "CFP4_SI5328_OUT1_BUF4_C_N"]
[get_ports "CFP4_SI5328_OUT1_BUF4_C_P"]
[get_ports "EXAMAX_SI5328_OUT1_BUF1_C_N"]
[get_ports "EXAMAX_SI5328_OUT1_BUF1_C_P"]
[get_ports "EXAMAX_SI5328_OUT1_BUF2_C_N"]
[get_ports "EXAMAX_SI5328_OUT1_BUF2_C_P"]
[get_ports "ILKN_SI5328_OUT2_BUF1_C_N"]
[get_ports "ILKN_SI5328_OUT2_BUF1_C_P"]
[get_ports "ILKN_SI5328_OUT2_BUF2_C_N"]
[get_ports "ILKN_SI5328_OUT2_BUF2_C_P"]
[get_ports "ILKN_SI5328_OUT2_BUF3_C_N"]
[get_ports "ILKN_SI5328_OUT2_BUF3_C_P"]
[get_ports "ILKN_SI5328_OUT2_BUF4_C_N"]
[get_ports "ILKN_SI5328_OUT2_BUF4_C_P"]
[get_ports "ILKN_SI5328_OUT2_BUF5_C_N"]
[get_ports "ILKN_SI5328_OUT2_BUF5_C_P"]
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