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The VCU110 evaluation board I2C bus topology overview is shown in
X-Ref Target - Figure 1-16
UTIL_3V3 to SYS_1V8
Level
MAXIM_CABLE_B
shifter
PMBUS_ALERT
always
enabled
UTIL_3V3 to VCC1V8_2A
Level
MAXIM_CABLE_B
shifter
w/OE
PMBUS_ALERT
SYSMON IIC
The TCA9548 U28 RESET_B pin 3 is connected to FPGA U1 bank 65 pin AR18 via
IMPORTANT:
level-shifter U44. The PCA9544 does not have a reset pin. FPGA pin AR18 LVCMOS18 net
IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to
U28.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
SYS_1V8
SYS_1V8 to UTIL_3V3
IIC 1
SYS Controller
VCC1V8_2A
FPGA
VCC1V8_2A to UTIL_3V3
X32
(0v)
SYSMON_DC
Figure 1-16: I2C Bus Topology Overview
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
Level
shifter
IIC_MAIN
always
enabled
UTL_3V3
IIC MUX2
PCA9544
UTIL_3V3 to SYS_1V8
UTL_3V3
TCA9548
IIC MUX1
Level
shifter
w/OE
Figure
1-16.
12V_SW
Maxim power
regulators
X10 – x18
PMBUS SDA,
SCL
Maxim
cable
PMBUS (UTIL_3V3)
X10 – x18
FMC HPC(UTIL_3V3)
xxx
FMC LPC(UTIL_3V3)
xxx
EEPROM(UTIL_3V3)
x50
x75
SI570 x1
x5D
Port Expander
x21
SI5328 ILKN/ExaMAX
x68
SI5328 CFP4
x69
SI5328 HMC
x6A
IIC HMC
x14
Level
shifter
SYSMON_IIC
X32
always
NOT USED
enabled
x74
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