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Table 1-26: VCU110 FPGA U1 GTH Quad 220 Connections (Cont'd)
FPGA (U1) Pin Name
MGTREFCLK0P_220
MGTREFCLK0N_220
MGTREFCLK1P_220
MGTREFCLK1N_220
Notes:
1. MGT connections I/O standard not applicable
Table 1-27: VCU110 FPGA U1 GTH Quad 221 Connections
FPGA (U1) Pin Name
MGTHTXP0_221
MGTHTXN0_221
MGTHRXP0_221
MGTHRXN0_221
MGTHTXP1_221
MGTHTXN1_221
MGTHRXP1_221
MGTHRXN1_221
MGTHTXP2_221
MGTHTXN2_221
MGTHRXP2_221
MGTHRXN2_221
MGTHTXP3_221
MGTHTXN3_221
MGTHRXP3_221
MGTHRXN3_221
MGTREFCLK0P_221
MGTREFCLK0N_221
MGTREFCLK1P_221
MGTREFCLK1N_221
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
(U1) Pin
AN11
NA
AN10
NA
AM13
NA
AM12
NA
FPGA
Schematic Net Name
(U1) Pin
BC7
FMC_HPC0_DP4_C2M_P
BC6
FMC_HPC0_DP4_C2M_N
BC2
FMC_HPC0_DP4_M2C_P
BC1
FMC_HPC0_DP4_M2C_N
BB9
FMC_HPC0_DP5_C2M_P
BB8
FMC_HPC0_DP5_C2M_N
BB4
FMC_HPC0_DP5_M2C_P
BB3
FMC_HPC0_DP5_M2C_N
BA7
FMC_HPC0_DP6_C2M_P
BA6
FMC_HPC0_DP6_C2M_N
BA2
FMC_HPC0_DP6_M2C_P
BA1
FMC_HPC0_DP6_M2C_N
AY9
FMC_HPC0_DP7_C2M_P
AY8
FMC_HPC0_DP7_C2M_N
AY4
FMC_HPC0_DP7_M2C_P
AY3
FMC_HPC0_DP7_M2C_N
AL11
FMC_HPC0_GBTCLK0_M2C_C_P
AL10
FMC_HPC0_GBTCLK0_M2C_C_N
AK13
FMC_HPC0_GBTCLK1_M2C_C_P
AK12
FMC_HPC0_GBTCLK1_M2C_C_N
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin Number
Name
NA
NA
NA
NA
Connected
Connected
(1)
Pin Number
A34
DP4_C2M_P
A35
DP4_C2M_N
A14
DP4_M2C_P
A15
DP4_M2C_N
A38
DP5_C2M_P
A39
DP5_C2M_N
A18
DP5_M2C_P
A19
DP5_M2C_N
B36
DP6_C2M_P
B37
DP6_C2M_N
B16
DP6_M2C_P
B17
DP6_M2C_N
B32
DP7_C2M_P
B33
DP7_C2M_N
B12
DP7_M2C_P
B13
DP7_M2C_N
(2)
D4
(2)
D5
(2)
B20
(2)
B21
Send Feedback
Connected
Device
NA
NA
NA
NA
NA
Connected
Pin Name
Device
FMC HPC0
J22
GBTCLK0_
M2C_P
GBTCLK0_
M2C_N
GBTCLK1_
M2C_P
GBTCLK1_
M2C_N
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