Xilinx VCU110 User Manual page 59

Table 1-24: VCU110 FPGA U1 GTY Quad 132 Connections
FPGA (U1) Pin Name
MGTYTXP0_132
MGTYTXN0_132
MGTYRXP0_132
MGTYRXN0_132
MGTYTXP1_132
MGTYTXN1_132
MGTYRXP1_132
MGTYRXN1_132
MGTYTXP2_132
MGTYTXN2_132
MGTYRXP2_132
MGTYRXN2_132
MGTYTXP3_132
MGTYTXN3_132
MGTYRXP3_132
MGTYRXN3_132
MGTREFCLK0P_132
MGTREFCLK0N_132
MGTREFCLK1P_132
MGTREFCLK1N_132
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
(U1) Pin
E40 ILKN_TX12_P
E41 ILKN_TX12_N
E45 ILKN_RX12_C_P
E46 ILKN_RX12_C_N
E36 ILKN_TX13_P
E37 ILKN_TX13_N
D43 ILKN_RX13_C_P
D44 ILKN_RX13_C_N
C40 ILKN_TX14_P
C41 ILKN_TX14_N
C45 ILKN_RX14_C_P
C46 ILKN_RX14_C_N
A40 ILKN_TX15_P
A41 ILKN_TX15_N
B43 ILKN_RX15_C_P
B44 ILKN_RX15_C_N
L36 ILKN_SI5328_OUT2_BUF4_C_P
L37 ILKN_SI5328_OUT2_BUF4_C_N
K34 NA
K35 NA
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Chapter 1: VCU110 Evaluation Board Features
Connected
(1)
Pin Number
F11
F12
(2)
G11
(2)
G12
H11
H12
(2)
J11
(2)
J12
F14
F15
(2)
J14
(2)
J15
H14
H15
(2)
J14
(2)
J15
(2)
35
(2)
34
NA
NA
Connected Connected
Pin Name Device
TX12_P
TX12_N
RX12_P
RX12_N
TX13_P
TX13_N
RX13_P
RX13_N
Interlaken
J121
TX14_P
TX14_N
RX14_P
RX14_N
TX15_P
TX15_N
RX15_P
RX15_N
CKOUT2_P
SI5328
U181
CKOUT2_N
NA
NA
NA
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