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Table 1-4: QDR2 Memory U168 18-bit SIO I/F to FPGA U1 Banks 66 and 67 (Cont'd)
FPGA (U1) Pin
AV24
AW22
BB24
BE23
BD23
BC23
BE24
BF22
BF21
BC24
BB23
BE22
BD22
BB22
BA24
BA25
AV23
AY25
AY22
AN24
AT25
AU23
AU24
AY23
BF24
AW25
AN28
AM29
AN29
AM31
AP28
AN31
AR27
AR29
AR30
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
QDR2_18B_A3
QDR2_18B_A4
QDR2_18B_A5
QDR2_18B_A6
QDR2_18B_A7
QDR2_18B_A8
QDR2_18B_A9
QDR2_18B_A10
QDR2_18B_A11
QDR2_18B_A12
QDR2_18B_A13
QDR2_18B_A14
QDR2_18B_A15
QDR2_18B_A16
QDR2_18B_A17
QDR2_18B_A18
QDR2_18B_A19
QDR2_18B_A20
QDR2_18B_A21
QDR2_18B_BWS0_B
QDR2_18B_BWS1_B
QDR2_18B_K_P
QDR2_18B_K_N
QDR2_18B_WPS_B
QDR2_18B_RPS_B
QDR2_18B_DOFF_B
QDR2_18B_Q0
QDR2_18B_Q1
QDR2_18B_Q2
QDR2_18B_Q3
QDR2_18B_Q4
QDR2_18B_Q5
QDR2_18B_Q6
QDR2_18B_Q7
QDR2_18B_Q8
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
I/O Standard
Pin Number
HSTL_I_DCI
B8
HSTL_I_DCI
C5
HSTL_I_DCI
C6
HSTL_I_DCI
C7
HSTL_I_DCI
N5
HSTL_I_DCI
N6
HSTL_I_DCI
N7
HSTL_I_DCI
P44
HSTL_I_DCI
P55
HSTL_I_DCI
P77
HSTL_I_DCI
P88
HSTL_I_DCI
R33
HSTL_I_DCI
R44
HSTL_I_DCI
R55
HSTL_I_DCI
R77
HSTL_I_DCI
R88
HSTL_I_DCI
R9
HSTL_I_DCI
A10
HSTL_I_DCI
A2
HSTL_I_DCI
B7
HSTL_I_DCI
A5
DIFF_HSTL_I_D
B6
DIFF_HSTL_I_D
A6
HSTL_I_DCI
A7
HSTI_I
A8
HSTL_I_DCI
H1
HSTL_I_DCI
P11
HSTL_I_DCI
M10
HSTL_I_DCI
L11
HSTL_I_DCI
K11
HSTL_I_DCI
J10
HSTL_I_DCI
F11
HSTL_I_DCI
E11
HSTL_I_DCI
C10
HSTL_I_DCI
B11
Pin Name
A3
A4
A5 (BL2/BL4)
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
NC_72M
NC_144M
BWS0_BS0_B_B
BWS1_BS1_B_B
K
K_B
WPS_B
RPS_B
DOFF_B
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
17
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