Xilinx VCU110 User Manual page 83

Table 1-45 details the FPGA U1 to U58 M88E111 Ethernet PHY connections.
Table 1-45: FPGA U1 to Ethernet PHY U58 Connections
FPGA (U1) Pin
BB21
BC18
BC21
BB18
Notes:
1. Ethernet PHY U58 signals are level-shifted (U45) to 1.8V for interface to FPGA U1 Bank 84.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Net Name I/O Standard
PHY_MDIO LVCMOS18
PHY_MDC LVCMOS18
PHY_INT LVCMOS18
PHY_RESET LVCMOS18
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Chapter 1: VCU110 Evaluation Board Features
M88E111 PHY U58
Pin Name
M1 MDIO_SDA
L3 MDC_SCL
L1 INT_B
K3 RESET_B
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