Programmable User Clock - Xilinx VCU110 User Manual

Programmable User Clock

[Figure 1-2, callout 11]
The VCU110 evaluation board has a SI570 programmable low-jitter LVDS differential
oscillator (U32). The U32 output drives clock pair USER_SI570_CLOCK_P and
USER_SI570_CLOCK_N, connected to XCVU190 FPGA U1 HR Bank 65 GC pins AY20 and
BA20, respectively.
On power-up, the U32 SI570 user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to 810 MHz
through an I2C interface. Power cycling the VCU110 evaluation board resets the user clock
to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency jitter: 50 ppm
• LVDS differential output
The programmable clock circuit is shown in
X-Ref Target - Figure 1-9
USER_SI570_CLOCK_SDA
USER_SI570_CLOCK_SCL
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Chapter 1:
Figure 1-9.
UTIL_3V3
1
4.70K
1/16W
2
1%
Si570BAB0000544DG
NC
1 NC
VDD
2
OE
OUT_B
3
GND OUT
GND
Figure 1-9: User Clock
www.xilinx.com
VCU110 Evaluation Board Features
UTIL_3V3
1
0.01 uF
2 25V
X7R
GND
6
USER_SI570_CLOCK_N
5
4 USER_SI570_CLOCK_P
50 ppm
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