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Table 1-5: RLD3 Memory U141 36-bit I/F to FPGA U1 Banks 70 and 71 (Cont'd)
FPGA (U1) Pin
B26
A28
C28
C29
B28
K29
J26
K28
N27
L28
K26
M27
K27
L29
H27
J27
G26
F29
G28
E27
E29
F26
F28
N29
N32
M30
N30
K31
M32
J32
J31
K32
E28
L30
D26
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
RLD3_36B_DQ4
RLD3_36B_DQ5
RLD3_36B_DQ6
RLD3_36B_DQ7
RLD3_36B_DQ8
RLD3_36B_DQ9
RLD3_36B_DQ10
RLD3_36B_DQ11
RLD3_36B_DQ12
RLD3_36B_DQ13
RLD3_36B_DQ14
RLD3_36B_DQ15
RLD3_36B_DQ16
RLD3_36B_DQ17
RLD3_36B_DQ18
RLD3_36B_DQ19
RLD3_36B_DQ20
RLD3_36B_DQ21
RLD3_36B_DQ22
RLD3_36B_DQ23
RLD3_36B_DQ24
RLD3_36B_DQ25
RLD3_36B_DQ26
RLD3_36B_DQ27
RLD3_36B_DQ28
RLD3_36B_DQ29
RLD3_36B_DQ30
RLD3_36B_DQ31
RLD3_36B_DQ32
RLD3_36B_DQ33
RLD3_36B_DQ34
RLD3_36B_DQ35
RLD3_36B_DM0
RLD3_36B_DM1
RLD3_36B_QK0_P
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
I/O Standard
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
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