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The connections between RLD3 component memory U173 and XCVU190 bank 72 are listed
in
Table
1-6.
Table 1-6: RLD3 Memory U173 18-bit I/F to FPGA U1 Bank 72
FPGA (U1) Pin
K16
L15
L20
L18
J16
L19
K18
M20
K19
N19
M16
M17
N20
P16
M15
P17
P20
P19
L16
N17
A20
F20
E18
H18
G18
H19
J19
F18
A19
H20
J20
E19
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Chapter 1:
Schematic Net Name
RLD3_18B_DQ0
RLD3_18B_DQ1
RLD3_18B_DQ2
RLD3_18B_DQ3
RLD3_18B_DQ4
RLD3_18B_DQ5
RLD3_18B_DQ6
RLD3_18B_DQ7
RLD3_18B_DQ8
RLD3_18B_DQ9
RLD3_18B_DQ10
RLD3_18B_DQ11
RLD3_18B_DQ12
RLD3_18B_DQ13
RLD3_18B_DQ14
RLD3_18B_DQ15
RLD3_18B_DQ16
RLD3_18B_DQ17
RLD3_18B_DM0
RLD3_18B_DM1
RLD3_18B_A0
RLD3_18B_A3
RLD3_18B_A4
RLD3_18B_A5
RLD3_18B_A8
RLD3_18B_A9
RLD3_18B_A10
RLD3_18B_A13
RLD3_18B_A14
RLD3_18B_A17
RLD3_18B_A18
RLD3_18B_BA0
www.xilinx.com
VCU110 Evaluation Board Features
I/O Standard
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
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