Xilinx VCU110 User Manual page 78

The CFP module J107-J110 connections to the GTY Quads 122, 125, 127 and 128 are
detailed in Table 1-40
Table 1-40: VCU110 FPGA U1 GTY Quad 122 Connections
FPGA (U1) Pin Name
MGTYTXP0_122
MGTYTXN0_122
MGTYRXP0_122
MGTYRXN0_122
MGTYTXP1_122
MGTYTXN1_122
MGTYRXP1_122
MGTYRXN1_122
MGTYTXP2_122
MGTYTXN2_122
MGTYRXP2_122
MGTYRXN2_122
MGTYTXP3_122
MGTYTXN3_122
MGTYRXP3_122
MGTYRXN3_122
MGTREFCLK0P_122
MGTREFCLK0N_122
MGTREFCLK1P_122
MGTREFCLK1N_122
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
through Table 1-42.
FPGA
Schematic Net Name
(U1) Pin
AW40 CFP4_MOD0_TX3_P
AW41 CFP4_MOD0_TX3_N
AW45 CFP4_MOD0_RX3_P
AW46 CFP4_MOD0_RX3_N
AV38 CFP4_MOD0_TX2_P
AV39 CFP4_MOD0_TX2_N
AV43 CFP4_MOD0_RX2_P
AV44 CFP4_MOD0_RX2_N
AU40 CFP4_MOD0_TX1_P
AU41 CFP4_MOD0_TX1_N
AU45 CFP4_MOD0_RX1_P
AU46 CFP4_MOD0_RX1_N
AT38 CFP4_MOD0_TX0_P
AT39 CFP4_MOD0_TX0_N
AT43 CFP4_MOD0_RX0_P
AT44 CFP4_MOD0_RX0_N
AJ36 CFP4_SI5328_OUT1_BUF1_C_P
AJ37 CFP4_SI5328_OUT1_BUF1_C_N
AH34 NA
AH35 NA
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Chapter 1: VCU110 Evaluation Board Features
Connected Connected
(1)
Pin Number Pin Name
54 TX3P--TX0P
55 TX3N--TX0N
39 RX3P--RX3N
40 RX3N--RX3P
51 TX2P--TX1P
52 TX2N--TX1N
36 RX2P--RX2N
37 RX2N--RX2P
48 TX1P--TX2P
49 TX1N--TX2N
33 RX1P--RX1N
34 RX1N--RX1P
45 TX0P--TX3P
46 TX0N--TX3N
30 RX0N--RX0P
31 RX0P--RX0N
(2)
28 CKOUT1_P
(2)
29 CKOUT1_N
NA
NA
Send Feedback
Connected
Device
CFP4
MOD0
J107
SI5328
U179
NA
NA
NA
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