Xilinx VCU118 User Manual
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Xilinx VCU118 User Manual

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VCU118 Evaluation Board
User Guide
UG1224 (v1.0) December 15, 2016

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Summary of Contents for Xilinx VCU118

  • Page 1 VCU118 Evaluation Board User Guide UG1224 (v1.0) December 15, 2016...

  • Page 2: Revision History

    Revision History The following table shows the revision history for this document. Date Version Revision 12/15/2016 Initial Xilinx release. VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 3: Table Of Contents

    Installing the VCU118 Board in a PC Chassis ....... . .

  • Page 4: Table Of Contents

    VCU118 Board Constraints File Listing ........

  • Page 5: Overview

    The VCU118 evaluation board for the Xilinx Virtex UltraScale+ FPGA provides a hardware environment for developing and evaluating designs targeting the UltraScale+ XCVU9P-L2FLGA2104 device. The VCU118 evaluation board provides features common to many evaluation systems, including: • DDR4 and RLD3 component memory •...

  • Page 6: Block Diagram

    Chapter 1: Introduction Block Diagram A block diagram of the VCU118 evaluation board is shown in Figure 1-1. X-Ref Target - Figure 1-1 X18010-100416 Figure 1-1: VCU118 Evaluation Board Block Diagram VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016...

  • Page 7: Board Features

    Chapter 1: Introduction Board Features The VCU118 evaluation board features are listed here. Detailed information for each feature is provided in Component Descriptions in Chapter • Virtex UltraScale+ XCVU9P-L2FLGA2104 device ® • Zynq -7000 AP SoC XC7Z010 based system controller •...

  • Page 8: Board Specifications

    Thickness (±5%): 0.061 inch (0.1549 cm) Length: 9.5 inch (24.13 cm) A 3D model of this board is not available. Note: The VCU118 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI IMPORTANT: ® Express card.

  • Page 9: Operating Voltage

    Chapter 1: Introduction Operating Voltage +12 V VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 10: Board Component Location

    IMPORTANT: board. The VCU118 board can be damaged by electrostatic discharge (ESD). Follow standard ESD CAUTION! prevention measures when handling the board. VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016...
  • Page 11 Round callout references a component Square callout references a component on the front side of the board on the backside side of the board X18022-102616 Figure 2-1: VCU118 Evaluation Board Components Table 2-1: VCU118 Board Component Descriptions Schematic Callout Feature...
  • Page 12 Chapter 2: Board Setup and Configuration Table 2-1: VCU118 Board Component Descriptions (Cont’d) Schematic Callout Feature Notes Page Number Linear BPI Flash Memory, BPI 16-bit Micron MT28GU01GAAA1EGC-0SIT configuration memory 1 Gb (U133) Micro-SD Card Interface, (bottom) Molex 5025700893 Micro-SD card interface connector (J83)
  • Page 13 Connectivity, lane 2x4 0.1 inch male header Sullins width select header, (J7) PBC36DAAN Notes: 1. The VCU118 board schematics are available for download. See the VCU118 Evaluation Kit. 2. The VCU118 board jumper header locations are shown in Figure 2-2.

  • Page 14: Default Switch And Jumper Settings

    Position 1, System Controller Enable SW16 4-pole configuration 0101 Positions 2-4, FPGA U1 mode M[2:0] Notes: 1. DIP switches are active-High (connected net is pulled High when DIP switch is closed). VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 15: Jumpers

    Chapter 2: Board Setup and Configuration Jumpers Figure 2-2 shows the VCU118 board jumper header locations. Each numbered component shown in the figure is keyed to Table 2-3, which identifies the default jumper settings and references the respective schematic page numbers.

  • Page 16: Installing The Vcu118 Board In A Pc Chassis

    Installation of the VCU118 board inside a computer chassis is required when developing or testing PCI Express® functionality. When the VCU118 board is used inside a computer chassis (that is, plugged in to the PCIe® slot), power is provided from the ATX power supply 4-pin peripheral connector through the...

  • Page 17: Fpga Configuration

    Figure 2-3. a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J15 on the VCU118 board. b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.
  • Page 18 For complete details on configuring the FPGA, see UltraScale Architecture Configuration User Guide (UG570) [Ref Figure 2-4 shows the configuration mode DIP switch SW16 default switch positions. X-Ref Target - Figure 2-4 Figure 2-4: SW16 Default Settings VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 19 Component Descriptions Virtex UltraScale+ XCVU9P-L2FLGA2104 Device [Figure 2-1, callout 1] The VCU118 board is populated with the Virtex UltraScale+ XCVU9P-L2FLGA2104 device. For more information on Virtex UltraScale+ FPGAs, see Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref...
  • Page 20 Chapter 3: Board Component Descriptions Encryption Key Battery Backup Circuit The XCVU9P device U1 implements bitstream encryption key technology. The VCU118 board provides the encryption key backup battery circuit shown in Figure 3-1. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XCVU9P device U1 VBATT pin AT11.
  • Page 21 Chapter 3: Board Component Descriptions I/O Voltage Rails There are 16 I/O banks available on the XCVU9P device and the VCU118 board. The voltages applied to the FPGA I/O banks used by the VCU118 board are listed in Table 3-1.

  • Page 22: Ddr4 Component Memory

    DQU5 DDR4_C1_DQ14 POD12_DCI DQU6 DDR4_C1_DQ15 POD12_DCI DQU7 DDR4_C1_DQS0_T DIFF_POD12_DCI DQSL_T DDR4_C1_DQS0_C DIFF_POD12_DCI DQSL_C DDR4_C1_DQS1_T DIFF_POD12_DCI DQSU_T DDR4_C1_DQS1_C DIFF_POD12_DCI DQSU_C DDR4_C1_DM0 POD12_DCI DML_B/DBIL_B DDR4_C1_DM1 POD12_DCI DMU_B/DBIU_B DDR4_C1_DQ16 POD12_DCI DQL0 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 23 DQL3 DDR4_C1_DQ36 POD12_DCI DQL4 DDR4_C1_DQ37 POD12_DCI DQL5 DDR4_C1_DQ38 POD12_DCI DQL6 DDR4_C1_DQ39 POD12_DCI DQL7 DDR4_C1_DQ40 POD12_DCI DQU0 DDR4_C1_DQ41 POD12_DCI DQU1 DDR4_C1_DQ42 POD12_DCI DQU2 DDR4_C1_DQ43 POD12_DCI DQU3 DDR4_C1_DQ44 POD12_DCI DQU4 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 24 DQU7 DDR4_C1_DQS6_T DIFF_POD12_DCI DQSL_T DDR4_C1_DQS6_C DIFF_POD12_DCI DQSL_C DDR4_C1_DQS7_T DIFF_POD12_DCI DQSU_T DDR4_C1_DQS7_C DIFF_POD12_DCI DQSU_C DDR4_C1_DM6 POD12_DCI DML_B/DBIL_B DDR4_C1_DM7 POD12_DCI DMU_B/DBIU_B DDR4_C1_DQ64 POD12_DCI DQL0 DDR4_C1_DQ65 POD12_DCI DQL1 DDR4_C1_DQ66 POD12_DCI DQL2 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 25 SSTL12_DCI U60-U64 DDR4_C1_A7 SSTL12_DCI U60-U64 DDR4_C1_A8 SSTL12_DCI U60-U64 DDR4_C1_A9 SSTL12_DCI U60-U64 DDR4_C1_A10 SSTL12_DCI A10/AP U60-U64 DDR4_C1_A11 SSTL12_DCI U60-U64 DDR4_C1_A12 SSTL12_DCI A12/BC_B U60-U64 DDR4_C1_A13 SSTL12_DCI U60-U64 DDR4_C1_BA0 SSTL12_DCI U60-U64 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 26 POD12_DCI DQL6 U135 BD31 DDR4_C2_DQ7 POD12_DCI DQL7 U135 BA32 DDR4_C2_DQ8 POD12_DCI DQU0 U135 BB33 DDR4_C2_DQ9 POD12_DCI DQU1 U135 BA30 DDR4_C2_DQ10 POD12_DCI DQU2 U135 BA31 DDR4_C2_DQ11 POD12_DCI DQU3 U135 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 27 DIFF_POD12_DCI DQSU_C U136 AP32 DDR4_C2_DQS3_C DIFF_POD12_DCI DQSU_T U136 AV33 DDR4_C2_DM2 POD12_DCI DML_B/DBIL_B U136 AR32 DDR4_C2_DM3 POD12_DCI DMU_B/DBIU_B U136 BE34 DDR4_C2_DQ32 POD12_DCI DQL0 U137 BF34 DDR4_C2_DQ33 POD12_DCI DQL1 U137 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 28 POD12_DCI DQU0 U138 AW36 DDR4_C2_DQ57 POD12_DCI DQU1 U138 AU40 DDR4_C2_DQ58 POD12_DCI DQU2 U138 AV40 DDR4_C2_DQ59 POD12_DCI DQU3 U138 AU38 DDR4_C2_DQ60 POD12_DCI DQU4 U138 AU39 DDR4_C2_DQ61 POD12_DCI DQU5 U138 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 29 DQSU_T U139 BE29 DDR4_C2_DM8 POD12_DCI DML_B/DBIL_B U139 BA29 DDR4_C2_DM9 POD12_DCI DMU_B/DBIU_B U139 AM27 DDR4_C2_A0 SSTL12_DCI U135-U139 AL27 DDR4_C2_A1 SSTL12_DCI U135-U139 AP26 DDR4_C2_A2 SSTL12_DCI U135-U139 AP25 DDR4_C2_A3 SSTL12_DCI U135-U139 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 30 U135-U139 AY35 DDR4_C2_TEN SSTL12_DCI U135-U139 The VCU118 dual DDR4 80-bit memory component interfaces adhere to the constraints guidelines documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 4]. The VCU118 board DDR4 memory component interface is a 40Ω...

  • Page 31: Rld3 Component Memory

    RLD3_C3_72B_DQ16 SSTL12 DQ16 U141 RLD3_C3_72B_DQ17 SSTL12 DQ17 U141 RLD3_C3_72B_DQ18 SSTL12 DQ18 U141 RLD3_C3_72B_DQ19 SSTL12 DQ19 U141 RLD3_C3_72B_DQ20 SSTL12 DQ20 U141 RLD3_C3_72B_DQ21 SSTL12 DQ21 U141 RLD3_C3_72B_DQ22 SSTL12 DQ22 U141 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 32 U141 RLD3_C3_72B_DQ36 SSTL12 U142 RLD3_C3_72B_DQ37 SSTL12 U142 RLD3_C3_72B_DQ38 SSTL12 U142 RLD3_C3_72B_DQ39 SSTL12 U142 RLD3_C3_72B_DQ40 SSTL12 U142 RLD3_C3_72B_DQ41 SSTL12 U142 RLD3_C3_72B_DQ42 SSTL12 U142 RLD3_C3_72B_DQ43 SSTL12 U142 RLD3_C3_72B_DQ44 SSTL12 U142 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 33 U142 RLD3_C3_72B_DQ71 SSTL12 DQ35 U142 RLD3_C3_72B_DM2 SSTL12 U142 RLD3_C3_72B_DM3 SSTL12 U142 RLD3_C3_72B_QK4_P DIFF_SSTL12 U142 RLD3_C3_72B_QK4_N DIFF_SSTL12 QK0_B U142 RLD3_C3_72B_QK5_P DIFF_SSTL12 U142 RLD3_C3_72B_QK5_N DIFF_SSTL12 QK1_B U142 RLD3_C3_72B_QK6_P DIFF_SSTL12 U142 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 34 U141-U142 RLD3_C3_72B_BA0 SSTL12 U141-U142 RLD3_C3_72B_BA1 SSTL12 U141-U142 RLD3_C3_72B_BA2 SSTL12 U141-U142 RLD3_C3_72B_BA3 SSTL12 U141-U142 RLD3_C3_72B_WE_B SSTL12 WE_B U141-U142 RLD3_C3_72B_REF_B SSTL12 REF_B U141-U142 RLD3_C3_72B_CK_P SSTL12 U141-U142 RLD3_C3_72B_CK_N SSTL12 CK_B U141-U142 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 35 Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 4]. The VCU118 RLD3 memory component interface is a 40Ω impedance implementation. For more information on the internal VREF, see the "Supply Voltages for the SelectIO Pins", “V ”, and “Internal V ”...

  • Page 36: Linear Bpi Flash Memory

    See the UltraScale Architecture Configuration User Guide (UG570) [Ref 2] for more information. Add these constraints for compression to designs targeted for the VCU118 board. • When loading from BPI flash: set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design] set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] set_property CONFIG_MODE BPI16 [current_design] *set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]...
  • Page 37 Chapter 3: Board Component Descriptions X-Ref Target - Figure 3-2 X18006-100416 Figure 3-2: Linear BPI 128 MB (1 Gbit) Flash Memory VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 38 LVCMOS18 AV18 BPI_FLASH_A7 LVCMOS18 AW18 BPI_FLASH_A8 LVCMOS18 AY18 BPI_FLASH_A9 LVCMOS18 AY19 BPI_FLASH_A10 LVCMOS18 BA19 BPI_FLASH_A11 LVCMOS18 BA17 BPI_FLASH_A12 LVCMOS18 BB17 BPI_FLASH_A13 LVCMOS18 BB19 BPI_FLASH_A14 LVCMOS18 BC19 BPI_FLASH_A15 LVCMOS18 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 39: Micro-Sd Card Interface

    [Figure 2-1, callout 7] The VCU118 board includes a secure digital input/output (SDIO) interface allowing the U111 XC7Z010 Zynq-7000 AP SoC system controller access to general purpose nonvolatile micro-SD memory cards and peripherals. The micro-SD card slot is designed to support 50 MHz high speed micro-SD cards.

  • Page 40: Digilent Usb Jtag Module

    (host side) to micro-B (VCU118 board side J106) USB cable. A 2 mm JTAG header (J3) is also provided in parallel for access by Xilinx download cables, such as the Platform Cable USB II. JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M[2:0], wired to SW16 positions [2:4].

  • Page 41: Fmc Connector Jtag Bypass

    Chapter 3: Board Component Descriptions FMC Connector JTAG Bypass When an FMC is attached to the VCU118 board, it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U26 (HSPC) and U132 (HPC1). The SPST switches are in a normally closed state and transition to an open state when the FMC is attached.
  • Page 42 MHz. U14 output drives U21 dual clock buffer. (250MHZ_CLK1_P/N and 250MHZ_CLK2_P/N) Table 3-7 lists the VCU118 clock sources to FPGA U1 connections. Table 3-7: VCU118 Clock Sources to XCVU9P FPGA U1 Connections Clock Source Schematic Net Name I/O Standard FPGA (U1) Pin Device/U#.Pin#...

  • Page 43: System Clock

    Chapter 3: Board Component Descriptions Table 3-7: VCU118 Clock Sources to XCVU9P FPGA U1 Connections (Cont’d) Clock Source Schematic Net Name I/O Standard FPGA (U1) Pin Device/U#.Pin# SMA/J35.1 USER_SMA_CLOCK_N LVDS SMA/U38.4 QSFP_SI570_CLOCK_P SMA/U38.5 QSFP_SI570_CLOCK_N ICS85411A/U21.1 250MHZ_CLK1_P LVDS ICS85411A/U21.2 250MHZ_CLK1_N LVDS ICS85411A/U21.3...
  • Page 44 3-4. X-Ref Target - Figure 3-4 X18004-102616 Figure 3-4: VCU118 System Clock The VCU118 SYSCLKn_300 clocks have an optional clock oscillator source U18 as shown in ² Figure 3-4. SI570 I C programmable low-jitter 3.3V LVDS differential oscillator U18 is connected to the CLK1 P/N inputs (pins 3 (P) and 4 (N)) of clock MUX/quad buffer SI53340 U157.

  • Page 45: Programmable User Clock 1

    On power-up, the U18 SI570 user clock defaults to an output frequency of 156.250 MHz. The system controller and user applications can change the output frequency within the range of 10 MHz to 810 MHz. Power cycling the VCU118 evaluation board resets the user clock to the default frequency of 156.250 MHz.
  • Page 46 The I²C programmable SI570 U32/SI53340 U104 clock buffer circuit is shown in Figure 3-5. X-Ref Target - Figure 3-5 X18003-100416 Figure 3-5: VCU118 Board User and MGT Clocks VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 47: Programmable User Clock 2 (Qsfp Clock)

    The Zynq-7000 AP SoC system controller or FPGA user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I²C interface. Power cycling the VCU118 evaluation board resets the user clock to the default frequency of 156.250 MHz.

  • Page 48: Mhz Clock

    250 MHz Clock [Figure 2-1, callout 14] The VCU118 evaluation board has an Epson SG5032 3.3V LVDS differential fixed 250 MHz oscillator (U14) connected to 1-to-2 ICS85411 clock buffer U21. The 3.3V ICS85411 U21 has two LVDS output clock pairs: •...

  • Page 49: User Sma Clock

    [Figure 2-1, callout 15] The VCU118 board provides a pair of SMAs for differential user clock input into FPGA U1 HP bank 45. The P-side SMA J34 signal USER_SMA_CLOCK_P is connected to FPGA U1 HP bank 45 GC pin R32, with the N-side SMA J35 signal USER_SMA_CLOCK_N connected to U1 HP bank 45 GC pin P32.

  • Page 50: Jitter Attenuated Clock

    [Figure 2-1, callout 16] The VCU118 board includes a Silicon Labs Si5328B jitter attenuator U57 on the back side of the board. The FPGA U1 QSFP1/QSFP2 control interface bank 64 can output QSFP RX differential clocks (QSFP1_RECCLK_P, pin AM23 and QSFP1_RECCLK_N, pin AM22, and QSFP2_RECCLK_P, pin AP23 and QSFP2_RECCLK_N, pin AP22) for jitter attenuation.
  • Page 51 Chapter 3: Board Component Descriptions X-Ref Target - Figure 3-9 X17999-100416 Figure 3-9: VCU118 Board QSFP Jitter Attenuated Clock The Silicon Labs Si5328 U57 pin 1 reset net SI5328_RST_B must be driven High to enable IMPORTANT: the device. U57 pin 1 net SI5328_RST_B is level-shifted to 1.8V by U3 and is connected to FPGA U1 bank 64 pin BC21.

  • Page 52: Gty Transceivers

    The reference clock for a quad can be sourced from the quad above or quad below the GTY quad of interest. Right Side Quads The six GTY quads on the right side of the VCU118 board have connectivity as listed here: Quad 120: •...
  • Page 53 Four GTY transceivers allocated to FMC+ HSPC DP[4:7] (J22) Quad 127: • MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_C_P/N (J22) • MGTREFCLK1 - FMCP_HSPC_GBT1_4_M2C_C_P/N (U39) • Four GTY transceivers allocated to FMC+ HSPC DP[16:19] (J22) VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 54 Chapter 3: Board Component Descriptions Table 3-8 through Table 3-13 list the VCU118 FPGA U1 GTY transceiver bank 120, 122, 123, 125, 126, 127 connections, respectively. Table 3-8: VCU118 FPGA U1 GTY Transceiver Bank 120 Connections FPGA FPGA (U1) Pin...
  • Page 55 Chapter 3: Board Component Descriptions Table 3-9: VCU118 FPGA U1 GTY Transceiver Bank 121 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected Schematic Net Name Bank (U1) Pin Name Name Device AT42 MGTYTXP0_121 FMCP_HSPC_DP0_C2M_P DP0_C2M_P AT43 MGTYTXN0_121 FMCP_HSPC_DP0_C2M_N DP0_C2M_N...
  • Page 56 Chapter 3: Board Component Descriptions Table 3-10: VCU118 FPGA U1 GTY Transceiver Bank 122 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AK42 MGTYTXP0_122 FMCP_HSPC_DP8_C2M_P DP8_C2M_P AK43 MGTYTXN0_122 FMCP_HSPC_DP8_C2M_N DP8_C2M_N AG45...
  • Page 57 Chapter 3: Board Component Descriptions Table 3-11: VCU118 FPGA U1 GTY Transceiver Bank 125 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device AC40 MGTYTXP0_125 FMCP_HSPC_DP12_C2M_P DP12_C2M_P AC41 MGTYTXN0_125 FMCP_HSPC_DP12_C2M_N DP12_C2M_N AC45...
  • Page 58 Chapter 3: Board Component Descriptions Table 3-12: VCU118 FPGA U1 GTY Transceiver Bank 126 Connections FPGA FPGA (U1) Pin Connected Connected Pin (U1) Schematic Net Name Connected Device Bank Name Name MGTYTXP0_126 FMCP_HSPC_DP4_C2M_P DP4_C2M_P MGTYTXN0_126 FMCP_HSPC_DP4_C2M_N DP4_C2M_N MGTYRXP0_126 FMCP_HSPC_DP4_M2C_P DP4_M2C_P...
  • Page 59 Chapter 3: Board Component Descriptions Table 3-13: VCU118 FPGA U1 GTY Transceiver Bank 127 Connections FPGA FPGA (U1) Pin Connected Connected Pin Connected (U1) Schematic Net Name Bank Name Name Device MGTYTXP0_127 FMCP_HSPC_DP16_C2M_P DP16_C2M_P MGTYTXN0_127 FMCP_HSPC_DP16_C2M_N DP16_C2M_N MGTYRXP0_127 FMCP_HSPC_DP16_M2C_P DP16_M2C_P...
  • Page 60 Chapter 3: Board Component Descriptions Left Side Quads The seven GTY quads on the left side of the VCU118 board have connectivity as listed here: Quad 224: • MGTREFCLK0 - not connected • MGTREFCLK1 - not connected • Four GTY transceivers allocated to PCIe lanes 15:12 Quad 225: •...
  • Page 61 Four GTY transceivers allocated to FIREFLY (J6) Table 3-14 through Table 3-20 list the VCU118 FPGA U1 GTY transceiver bank 224, 225, 226, 227, 231, 232 and 233 connections, respectively. Table 3-14: VCU118 FPGA U1 GTY Transceiver Bank 224 Connections FPGA...
  • Page 62 Chapter 3: Board Component Descriptions Table 3-15: VCU118 FPGA U1 GTY Transceiver Bank 225 Connections FPGA FPGA (U1) Pin Name Schematic Net Name Connected Connected (U1) Connected Device Bank Pin Name MGTYTXP0_225 PCIE_TX11_P HSIP(11) MGTYTXN0_225 PCIE_TX11_N HSIN(11) MGTYRXP0_225 PCIE_RX11_P HSOP(11)
  • Page 63 Chapter 3: Board Component Descriptions Table 3-16: VCU118 FPGA U1 GTY Transceiver Bank 226 Connections FPGA Schematic Net Connected Pin Connected (U1) FPGA (U1) Pin Name Connected Pin Bank Name Name Device MGTYTXP0_226 PCIE_TX7_P HSIP(7) MGTYTXN0_226 PCIE_TX7_N HSIN(7) MGTYRXP0_226 PCIE_RX7_P...
  • Page 64 Chapter 3: Board Component Descriptions Table 3-17: VCU118 FPGA U1 GTY Transceiver Bank 227 Connections FPGA FPGA (U1) Pin Name Schematic Net Connected Pin Connected (U1) Connected Pin Bank Name Name Device MGTYTXP0_227 PCIE_TX3_P HSIN(3) MGTYTXN0_227 PCIE_TX3_N HSIP(3) MGTYRXP0_227 PCIE_RX3_P...
  • Page 65 Chapter 3: Board Component Descriptions Table 3-18: VCU118 FPGA U1 GTY Transceiver Bank 231 Connections FPGA FPGA (U1) Pin Name Schematic Net Name Connected Connected Pin Connected (U1) Bank Name Device MGTYTXP0_231 QSFP1_TX1_P TX1P MGTYTXN0_231 QSFP1_TX1_N TX1N MGTYRXP0_231 QSFP1_RX1_P RX1P...
  • Page 66 Chapter 3: Board Component Descriptions Table 3-19: VCU118 FPGA U1 GTY Transceiver Bank 232 Connections FPGA Connected Connected Pin Connected (U1) FPGA (U1) Pin Name Schematic Net Name Bank Name Device MGTYTXP0_232 QSFP2_TX1_P TX1P MGTYTXN0_232 QSFP2_TX1_N TX1N MGTYRXP0_232 QSFP2_RX1_P RX1P...
  • Page 67 Chapter 3: Board Component Descriptions Table 3-20: VCU118 FPGA U1 GTY Transceiver Bank 233 Connections FPGA Connected Connected Pin Connected (U1) Pin FPGA (U1) Pin Name Schematic Net Name Bank Name Device MGTYTXP0_233 FIREFLY_TX1_P TX1P MGTYTXN0_233 FIREFLY_TX1_N TX1N MGTYRXP0_233 FIREFLY_RX1_P...

  • Page 68: Pci Express Endpoint Connectivity

    The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The XCVU9P-L2FLGA2104 (-2 speed grade) is deployed on the VCU118 to support up to Gen3 x8.
  • Page 69 Figure 3-12: PCI Express Lane Size Select Jumper J7 Table 3-21 lists the PCIe U2 edge connector wiring to FPGA U1. Table 3-21: VCU118 Board FPGA U1 to PCIe Edge U2 Connections PCIe Edge U2 FPGA (U1) Pin Schematic Net...
  • Page 70 Chapter 3: Board Component Descriptions Table 3-21: VCU118 Board FPGA U1 to PCIe Edge U2 Connections (Cont’d) PCIe Edge U2 FPGA (U1) Pin Schematic Net FPGA (U1) Pin Name Name Pin Num Pin Name MGTYTXN3_226 PCIE_TX4_N HSIN(4) MGTYTXP2_226 PCIE_TX5_P HSIP(5)
  • Page 71 Chapter 3: Board Component Descriptions Table 3-21: VCU118 Board FPGA U1 to PCIe Edge U2 Connections (Cont’d) PCIe Edge U2 FPGA (U1) Pin Schematic Net FPGA (U1) Pin Name Name Pin Num Pin Name MGTYRXN2_226 PCIE_RX5_N HSON(5) MGTYRXP1_226 PCIE_RX6_P HSOP(6)

  • Page 72: Gb/S Qsfp+ Module Connectors

    [Figure 2-1, callout 18] The VCU118 board contains two quad (4-channel) small form-factor pluggable (28 Gb/s QSFP+) connectors, QSFP1 U145 and QSFP2 U123, which accept 28 Gb/s QSFP+ optical modules. Each connector is housed within a single 28 Gb/s QSFP+ cage assembly.
  • Page 73 Chapter 3: Board Component Descriptions The connections between the 28 Gb/s QSFP+ module connector U145 and the FPGA are listed in Table 3-22. Table 3-22: VCU118 Board FPGA U1 to QSFP+ Module QSFP1 U145 Connections QSFP1 U145 FPGA Schematic Net FPGA (U1)
  • Page 74 Chapter 3: Board Component Descriptions Table 3-23: VCU118 Board FPGA U1 to QSFP+ Module QSFP2 U123 Connections QSFP2 U123 FPGA FPGA (U1) FPGA (U1) Pin Name Schematic Net Name (U1) Pin Direction Pin Num Pin Name MGTYTXP0_232 QSFP2_TX1_P Output TX1P...

  • Page 75: Firefly Connector

    [Figure 2-1, callout 41] The VCU118 board contains a 4x28 Gb/s FireFly composite connector pair J6. The FireFly connector system is a two part connector designed for applications up to 28 Gb/s. It is based on two connectors, a micro high-speed edge connector (UEC5 Series, shown rear left) with two rows of 19 positions providing 12 differential lanes and a 10-position positive latch control signal and power connector (UCC8 Series, shown front right).
  • Page 76 Chapter 3: Board Component Descriptions Figure 3-15 shows the schematic representation. X-Ref Target - Figure 3-15 X17995-100416 Figure 3-15: FireFly Connector Schematic VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 77 Chapter 3: Board Component Descriptions The connections between the J6 and the FPGA are listed in Table 3-24. Table 3-24: VCU118 Board FPGA U1 to FireFly J6 Connections FireFly J6 FPGA FPGA (U1) FPGA (U1) Pin Name Schematic Net Name...

  • Page 78: Mb/S Tri-Speed Ethernet Phy

    [Figure 2-1, callout 19] The VCU118 evaluation board uses the TI PHY device DP83867ISRGZ (U7) for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only. The PHY connection to a user-provided Ethernet cable is through RJ-45 connector J10, a Wurth 7499111221A with built-in magnetics and status LEDs.

  • Page 79: Ethernet Phy Status Leds

    Two Ethernet PHY status LEDs are integrated into the metal frame of the J10 RJ-45 connector. These LEDs are visible on the left edge of the VCU118 board when it is installed into a PCIe slot in a PC chassis. The two PHY status LEDs are visible within the frame of the...

  • Page 80: Dual Usb-To-Uart Bridge

    VCU118 evaluation kit (standard type-A end to host computer, type micro-B end to VCU118 evaluation board connector J4). The CP2105GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VCU118 evaluation board.

  • Page 81: I2C Bus, Topology, And Switches

    For more technical information on the CP2105GM and the VCP drivers, see the Silicon Labs website [Ref 12]. Xilinx UART IP is expected to be implemented in the FPGA logic using IP. See the AXI UART Lite LogiCORE IP Product Guide (PG142) [Ref 10] for more information.
  • Page 82 0x74 SYSMON IIC X18025-102616 Figure 3-18: VCU118 IIC Bus The TCA9548 U28 and U80 RESET_B pin 3 is connected to FPGA U1 Bank 64 pin AL25. IMPORTANT: FPGA pin AL25 LVCMOS18 net IIC_MUX_RESET_B must be driven High to enable I²C bus transactions with the devices connected to U28 and U80.

  • Page 83: Status And User Leds

    [Ref 25]. Status and User LEDs [Figure 2-1, callouts 24] Table 3-28 defines VCU118 board status and user LEDs. Table 3-28: VCU118 Board Status and User LEDs Reference Designator Description ENET PHY link FPGA INIT Combined power good SYS_2V2 ON...
  • Page 84 Chapter 3: Board Component Descriptions Table 3-28: VCU118 Board Status and User LEDs (Cont’d) Reference Designator Description DS14 UTIL_3V3 On DS15 MGTAVCC On DS16 VCC1V2 On DS17 MGTAVTT On DS18 GPIO_LED_7 DS19 VADJ_1V8 On DS20 12V power available at power input jack J15...

  • Page 85: User I/O

    Chapter 3: Board Component Descriptions User I/O [Figure 2-1, callouts 24, 25, 26] The VCU118 board provides these user and general purpose I/O capabilities: • Eight user LEDs (callout 24) GPIO_LED[7-0]: DS31, DS32, DS33, DS10, DS19, DS8, DS6, DS7 °...

  • Page 86: User Pushbuttons

    Chapter 3: Board Component Descriptions User Pushbuttons [Figure 2-1, callout 25] Figure 3-20 shows the user pushbuttons circuit. X-Ref Target - Figure 3-20 X17991-100416 Figure 3-20: User Pushbuttons VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 87: Cpu Reset Pushbutton

    Figure 3-21: CPU Reset Pushbutton GPIO DIP Switch [Figure 2-1, callout 26] Figure 3-22 shows the GPIO DIP switch circuit. X-Ref Target - Figure 3-22 X17989-100416 Figure 3-22: GPIO DIP Switch VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 88 Chapter 3: Board Component Descriptions Table 3-29 lists the GPIO connections to FPGA U1. Table 3-29: VCU118 GPIO Connections to FPGA U1 Schematic Net FPGA (U1) FPGA (U1) Pin I/O Standard Device Name Direction GPIO LEDs (Active-High) GPIO_LED signals are wired to FET LED drivers...

  • Page 89: User Pmod Gpio Headers

    [Figure 2-1, callout 29] The VCU118 evaluation board supports two Pmod GPIO headers J52 and J53. The Pmod nets connected to these headers are accessed using level shifters U41 (PMOD0 J52) and U42 (PMOD1 J53). The level shifters are wired to XCVU9P FPGA U1 banks 47 and 67.
  • Page 90 J53.4 PMOD1_6_LS LVCMOS12 U42.9 U42.12 PMOD1_6 J53.6 PMOD1_7_LS LVCMOS12 U42.10 U42.11 PMOD1_7 J53.8 For more information about Pmod connector compatible Pmod modules, see the Digilent website [Ref 21]. VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 91: Switches

    [Figure 2-1, callout 30] The VCU118 board power switch is SW1. Sliding the switch actuator from the off to on position applies 12VDC power from the 6-pin mini-fit power input connector J15. Green LED DS20 illuminates when power is available at the VCU118 power connector J15, and DS26 illuminates when the VCU118 board power switch is on.
  • Page 92 The VCU118 evaluation kit provides the adapter cable shown in Figure 3-24 for powering the VCU118 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to the Sourcegate Technologies part number AZCBL-WH-1109-RA4. See [Ref 29] for ordering information.

  • Page 93: Fpga Mezzanine Card Interface

    J2 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400 pins. The connector is keyed so that a mezzanine card, when installed on the VCU118 evaluation board, faces away from the board.
  • Page 94 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33]) • Ten GTH transceiver differential pairs • Two GTH transceiver clocks • Two differential clocks • 159 ground and 15 power connections VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 95 LVDS AL15 VCC12_SW FMC_HPC1_TCK_BUF (2) U19.16 U132.1,U VCC12_SW FMCP_HSPC_TDO_HPC1_TDI (3) 26.2,J22. U132.2,U UTIL_3V3 FMC_HPC1_TDO (3) 13.8 UTIL_3V3 FMC_HPC1_TMS_BUF (2) U19.19 GA1 = 0 = GND UTIL_3V3 UTIL_3V3 UTIL_3V3 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 96 LVDS AV10 FMC_HPC1_LA31_N LVDS AM12 FMC_HPC1_LA28_N LVDS AW10 FMC_HPC1_LA33_P LVDS AK14 FMC_HPC1_LA30_P LVDS AK12 FMC_HPC1_LA33_N LVDS AK13 FMC_HPC1_LA30_N LVDS AL12 VADJ_1V8_FPGA FMC_HPC1_LA32_P LVDS AJ13 FMC_HPC1_LA32_N LVDS AJ12 VADJ_1V8_FPGA VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 97 FMCP) specification by providing a subset implementations of the high pin count connectors at J22 (HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so that a mezzanine card, when installed on the VCU118 evaluation board, faces away from the board.
  • Page 98 116 single-ended or 58 differential user-defined pairs (34 LA pairs: LA[00:33], 24 HA pairs: HA[00:23]) • 24 transceiver differential pairs • 6 transceiver differential clocks • 2 differential clocks • 239 ground and 16 power connections VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 99 FMCP_HSPC_DP8_C2M_P LVDS AK42 FMCP_HSPC_DP3_C2M_P LVDS AL40 FMCP_HSPC_DP8_C2M_N LVDS AK43 FMCP_HSPC_DP3_C2M_N LVDS AL41 FMCP_HSPC_DP7_C2M_P LVDS FMCP_HSPC_DP4_C2M_P LVDS FMCP_HSPC_DP7_C2M_N LVDS FMCP_HSPC_DP4_C2M_N LVDS FMCP_HSPC_DP6_C2M_P LVDS FMCP_HSPC_DP5_C2M_P LVDS FMCP_HSPC_DP6_C2M_N LVDS FMCP_HSPC_DP5_C2M_N LVDS VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 100 LVDS FMCP_HSPC_LA27_N LVDS FMCP_HSPC_LA23_P LVDS FMCP_HSPC_IIC_SCL FMCP_HSPC_LA23_N LVDS FMCP_HSPC_IIC_SDA FMCP_HSPC_LA26_P LVDS GA0 GND FMCP_HSPC_LA26_N LVDS VCC12_SW FMCP_HSPC_TCK_BUF VCC12_SW FPGA_TDO_FMC_TDI_BUF UTIL_3V3 FMCP_HSPC_TDO_HPC1_TDI UTIL_3V3 FMCP_HSPC_TMS_BUF GA1 GND UTIL_3V3 UTIL_3V3 UTIL_3V3 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 101 FMCP_HSPC_HA13_P LVDS FMCP_HSPC_HA08_N LVDS FMCP_HSPC_HA13_N LVDS FMCP_HSPC_HA12_P LVDS FMCP_HSPC_HA16_P LVDS FMCP_HSPC_HA12_N LVDS FMCP_HSPC_HA16_N LVDS FMCP_HSPC_HA15_P LVDS FMCP_HSPC_HA20_P LVDS FMCP_HSPC_HA15_N LVDS FMCP_HSPC_HA20_N LVDS FMCP_HSPC_HA19_P LVDS FMCP_HSPC_HA19_N LVDS VADJ_1V8_FPGA VADJ_1V8_FPGA VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 102 FMCP_HSPC_LA24_P LVDS FMCP_HSPC_LA29_N LVDS FMCP_HSPC_LA24_N LVDS FMCP_HSPC_LA31_P LVDS FMCP_HSPC_LA28_P LVDS FMCP_HSPC_LA31_N LVDS FMCP_HSPC_LA28_N LVDS FMCP_HSPC_LA33_P LVDS FMCP_HSPC_LA30_P LVDS FMCP_HSPC_LA33_N LVDS FMCP_HSPC_LA30_N LVDS VADJ_1V8_FPGA FMCP_HSPC_LA32_P LVDS FMCP_HSPC_LA32_N LVDS VADJ_1V8_FPGA VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 103 FMCP_HSPC_HA10_P LVDS FMCP_HSPC_HA14_P LVDS FMCP_HSPC_HA10_N LVDS FMCP_HSPC_HA14_N LVDS FMCP_HSPC_HA17_CC_P LVDS FMCP_HSPC_HA18_P LVDS FMCP_HSPC_HA17_CC_N LVDS FMCP_HSPC_HA18_N LVDS FMCP_HSPC_HA21_P LVDS FMCP_HSPC_HA22_P LVDS FMCP_HSPC_HA21_N LVDS FMCP_HSPC_HA22_N LVDS FMCP_HSPC_HA23_P LVDS FMCP_HSPC_HA23_N LVDS VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 104 FMCP_HSPC_REFCLK_M2C_N LVDS AL34 FMCP_HSPC_DP16_C2M_P LVDS FMCP_HSPC_SYNC_M2C_P LVDS AM36 FMCP_HSPC_DP16_C2M_N LVDS FMCP_HSPC_SYNC_M2C_N LVDS AN36 FMCP_HSPC_DP17_C2M_P LVDS FMCP_HSPC_DP17_C2M_N LVDS FMCP_HSPC_DP18_C2M_P LVDS VCC12_SW FMCP_HSPC_DP18_C2M_N LVDS VCC12_SW FMCP_HSPC_DP19_C2M_P LVDS VCC12_SW FMCP_HSPC_DP19_C2M_N LVDS VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 105 LVDS AC40 FMCP_HSPC_DP13_C2M_P LVDS AA40 FMCP_HSPC_DP12_C2M_N LVDS AC41 FMCP_HSPC_DP13_C2M_N LVDS AA41 FMCP_HSPC_DP16_M2C_P LVDS FMCP_HSPC_DP17_M2C_P LVDS FMCP_HSPC_DP16_M2C_N LVDS FMCP_HSPC_DP17_M2C_N LVDS FMCP_HSPC_DP18_M2C_P LVDS FMCP_HSPC_DP19_M2C_P LVDS FMCP_HSPC_DP18_M2C_N LVDS FMCP_HSPC_DP19_M2C_N LVDS UTIL_3V3 VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 106: Vcu118 Board Power System

    Chapter 3: Board Component Descriptions VCU118 Board Power System [Figure 2-1, callout 31] The VCU118 hosts a Maxim PMBus based power system. Figure 3-27 shows the VCU118 power system block diagram. X-Ref Target - Figure 3-27 X17984-100416 Figure 3-27: VCU118 Power System Block Diagram...
  • Page 107 Chapter 3: Board Component Descriptions The VCU118 evaluation board uses power regulators and PMBus compliant point of load (POL) controllers from Maxim Integrated Circuits to supply the core and auxiliary voltages listed in Table 3-33. Table 3-33: Onboard Power System Devices...

  • Page 108: Fmc Vadj_1V8 Power Rail

    1.2V, 1.5V, 1.8V, and 0.0V. • When two FMC cards are attached with differing VADJ requirements, VADJ_1V8 is set to the lowest value compatible with the VCU118 board and the FMC modules, within the available choices of 1.2V, 1.5V, 1.8V, and 0.0V. •...
  • Page 109 Chapter 3: Board Component Descriptions The Maxim PMBus controller and INA226 power monitor I C bus mapping is shown in Table 3-34. Table 3-34: VCU118 Voltage Regulators and INA226 Power Monitors PMBus Regulators and INA226 Map Schematic Vout PMBus INA226...

  • Page 110: Cooling Fan

    The XCVU9P FPGA U1 cooling fan connector is shown in Figure 3-28. The VCU118 fan circuit uses a Maxim MAX6643 fan controller that autonomously monitors the FPGA die temperature pins DXP and DXN. The fan circuit is set up to increase fan speed as the FPGA temperature increases.

  • Page 111: System Controller

    [Figure 2-1, callout 36] The VCU118 board includes an onboard Zynq-7000 AP SoC as the system controller. A host PC resident graphical user interface for the system controller (SCUI) is provided on the VCU118 website. The SCUI can be used to query and control select programmable features such as clocks, FMC functionality, and power systems.

  • Page 112: Configuration Options

    See Figure 3-29. See the VCU118 System Controller Tutorial (XTP447) and the VCU118 Software Install and Board Setup Tutorial (XTP449) for more information on installing and using the System Controller utility.
  • Page 113 Si5335A U122 is wired to the EMCCLK pin of the FPGA on bank 65 pin AL20. This allows the creation of bitstreams to configure the FPGA over the 16-bit datapath from the linear BPI flash memory at a maximum synchronous read rate of 90 MHz. VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016...
  • Page 114 Figure A-1 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) J2 defined by the VITA 57.1 FMC specification. For a description of how the VCU118 evaluation board implements the FMC specification, see FPGA Mezzanine Card Interface, page...
  • Page 115 Figure A-2 shows the pinout of the FPGA mezzanine card plus (FMCP) connector J22 defined by the VITA 57.4 FMC specification. For a description of how the VCU118 evaluation board implements the FMC specification, see FPGA Mezzanine Card Interface, page...
  • Page 116 Master Constraints File Listing Overview The master Xilinx design constraints (XDC) file template for the VCU118 board provides for designs targeting the VCU118 evaluation board. Net names in the constraints listed correlate with net names on the latest VCU118 evaluation board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL.
  • Page 117 LVDS [get_ports "USER_SI570_CLOCK_P"]; set_property PACKAGE_PIN [get_ports "USER_SI570_CLOCK_N "]; set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK_N"]; set_property PACKAGE_PIN AW23 [get_ports "USER_SI570_CLOCK1_P"]; set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_P"]; set_property PACKAGE_PIN AW22 [get_ports "USER_SI570_CLOCK1_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 118 [get_ports "DDR4_C1_DQ10"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ10"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ11"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ11"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ12"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ12"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ13"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 119 [get_ports "DDR4_C1_DQ29"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ29"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ30"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ30"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ31"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ31"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ32"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 120 [get_ports "DDR4_C1_DQ48"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ48"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ49"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ49"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ50"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ50"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ51"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 121 [get_ports "DDR4_C1_DQ67"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ67"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ68"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ68"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ69"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ69"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQ70"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 122 [get_ports "DDR4_C1_A6 "]; set_property PACKAGE_PIN [get_ports "DDR4_C1_A7 "]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A7 "]; set_property PACKAGE_PIN [get_ports "DDR4_C1_A8 "]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A8 "]; set_property PACKAGE_PIN [get_ports "DDR4_C1_A9 "]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 123 [get_ports "DDR4_C1_DM5"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM5"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DM6"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM6"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DM7"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM7"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DM8"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 124 [get_ports "DDR4_C1_DQS7_C"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS7_C"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQS7_T"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS7_T"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQS8_C"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS8_C"]; set_property PACKAGE_PIN [get_ports "DDR4_C1_DQS8_T"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 125 BD32 [get_ports "DDR4_C2_DQ2"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ2"]; set_property PACKAGE_PIN BE33 [get_ports "DDR4_C2_DQ3"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ3"]; set_property PACKAGE_PIN BC33 [get_ports "DDR4_C2_DQ4"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ4"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 126 AU32 [get_ports "DDR4_C2_DQ21"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ21"]; set_property PACKAGE_PIN AU31 [get_ports "DDR4_C2_DQ22"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ22"]; set_property PACKAGE_PIN AV31 [get_ports "DDR4_C2_DQ23"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ23"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 127 BD37 [get_ports "DDR4_C2_DQ40"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ40"]; set_property PACKAGE_PIN BE38 [get_ports "DDR4_C2_DQ41"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ41"]; set_property PACKAGE_PIN BC39 [get_ports "DDR4_C2_DQ42"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ42"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 128 AV40 [get_ports "DDR4_C2_DQ59"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ59"]; set_property PACKAGE_PIN AU38 [get_ports "DDR4_C2_DQ60"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ60"]; set_property PACKAGE_PIN AU39 [get_ports "DDR4_C2_DQ61"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ61"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 129 [get_ports "DDR4_C2_DQ78"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ78"]; set_property PACKAGE_PIN BB27 [get_ports "DDR4_C2_DQ79"]; set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ79"]; set_property PACKAGE_PIN AM27 [get_ports "DDR4_C2_A0 "]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A0 "]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 130 AR25 [get_ports "DDR4_C2_BA0"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BA0"]; set_property PACKAGE_PIN AU28 [get_ports "DDR4_C2_BA1"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BA1"]; set_property PACKAGE_PIN AU27 [get_ports "DDR4_C2_BG0"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BG0"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 131 AP32 [get_ports "DDR4_C2_DQS3_C"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS3_C"]; set_property PACKAGE_PIN AP31 [get_ports "DDR4_C2_DQS3_T"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS3_T"]; set_property PACKAGE_PIN BF35 [get_ports "DDR4_C2_DQS4_C"]; set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS4_C"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 132 BB29 [get_ports "DDR4_C2_ODT"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_ODT"]; set_property PACKAGE_PIN BF29 [get_ports "DDR4_C2_PAR"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_PAR"]; set_property PACKAGE_PIN AY35 [get_ports "DDR4_C2_TEN"]; set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_TEN"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 133 [get_ports "RLD3_C3_72B_DQ12"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ12"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ13"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ13"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ14"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ14"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ15"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 134 [get_ports "RLD3_C3_72B_DQ31"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ31"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ32"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ32"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ33"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ33"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ34"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 135 [get_ports "RLD3_C3_72B_DQ50"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ50"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ51"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ51"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ52"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ52"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ53"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 136 [get_ports "RLD3_C3_72B_DQ69"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ69"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ70"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ70"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DQ71"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ71"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_A0"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 137 [get_ports "RLD3_C3_72B_A16"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A16"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_A17"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A17"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_A18"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A18"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_A19"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 138 [get_ports "RLD3_C3_72B_DK3_N"]; set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_N"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_DK3_P"]; set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_P"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_QK0_N"]; set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_N"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_QK0_P"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 139 [get_ports "RLD3_C3_72B_QVLD1"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD1"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_QVLD2"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD2"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_QVLD3"]; set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD3"]; set_property PACKAGE_PIN [get_ports "RLD3_C3_72B_CK_P"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 140 LVCMOS18 [get_ports "BPI_FLASH_D9"]; set_property PACKAGE_PIN AR18 [get_ports "BPI_FLASH_D10"]; set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_D10"]; set_property PACKAGE_PIN AR17 [get_ports "BPI_FLASH_D11"]; set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_D11"]; set_property PACKAGE_PIN AT20 [get_ports "BPI_FLASH_D12"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 141 LVCMOS18 [get_ports "BPI_FLASH_A12"]; set_property PACKAGE_PIN BB17 [get_ports "BPI_FLASH_A13"]; set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_A13"]; set_property PACKAGE_PIN BB19 [get_ports "BPI_FLASH_A14"]; set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_A14"]; set_property PACKAGE_PIN BC19 [get_ports "BPI_FLASH_A15"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 142 [get_ports "BPI_WAIT "]; #FMCP HSPC set_property PACKAGE_PIN AM32 [get_ports "FMCP_HSPC_CLK0_M2C_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"]; set_property PACKAGE_PIN AL32 [get_ports "FMCP_HSPC_CLK0_M2C_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_CLK1_M2C_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 143 LVDS [get_ports "FMCP_HSPC_LA06_P"]; set_property PACKAGE_PIN AP37 [get_ports "FMCP_HSPC_LA07_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"]; set_property PACKAGE_PIN AP36 [get_ports "FMCP_HSPC_LA07_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"]; set_property PACKAGE_PIN AK30 [get_ports "FMCP_HSPC_LA08_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 144 IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"]; set_property PACKAGE_PIN AG34 [get_ports "FMCP_HSPC_LA16_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_LA17_CC_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_LA17_CC_P"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 145 [get_ports "FMCP_HSPC_LA25_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_LA26_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_LA26_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_LA27_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 146 [get_ports "FMCP_HSPC_HA00_CC_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA01_CC_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA01_CC_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA02_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 147 [get_ports "FMCP_HSPC_HA10_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA10_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA11_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA11_P"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 148 [get_ports "FMCP_HSPC_HA19_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA20_N"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_N"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA20_P"]; set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_P"]; set_property PACKAGE_PIN [get_ports "FMCP_HSPC_HA21_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 149 PACKAGE_PIN AL36 [get_ports "FMCP_HSPC_PG_M2C_LS"]; set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_PG_M2C_LS"]; set_property PACKAGE_PIN AL35 [get_ports "FMCP_HSPC_PRSNT_M2C_B_LS"]; set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_PRSNT_M2C_B_LS"]; # FMC HPC1 set_property PACKAGE_PIN [get_ports "FMC_HPC1_PG_M2C_LS "]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 150 LVDS [get_ports "FMC_HPC1_LA04_P"]; set_property PACKAGE_PIN BF14 [get_ports "FMC_HPC1_LA05_N"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_N"]; set_property PACKAGE_PIN BE14 [get_ports "FMC_HPC1_LA05_P"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_P"]; set_property PACKAGE_PIN BE13 [get_ports "FMC_HPC1_LA06_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 151 IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_N"]; set_property PACKAGE_PIN [get_ports "FMC_HPC1_LA14_P"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_P"]; set_property PACKAGE_PIN BC16 [get_ports "FMC_HPC1_LA15_N"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_N"]; set_property PACKAGE_PIN BB16 [get_ports "FMC_HPC1_LA15_P"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 152 LVDS [get_ports "FMC_HPC1_LA23_P"]; set_property PACKAGE_PIN AR12 [get_ports "FMC_HPC1_LA24_N"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_N"]; set_property PACKAGE_PIN AP12 [get_ports "FMC_HPC1_LA24_P"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_P"]; set_property PACKAGE_PIN AU12 [get_ports "FMC_HPC1_LA25_N"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 153 [get_ports "FMC_HPC1_LA32_P"]; set_property PACKAGE_PIN AK13 [get_ports "FMC_HPC1_LA33_N"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_N"]; set_property PACKAGE_PIN AK14 [get_ports "FMC_HPC1_LA33_P"]; set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_P"]; # IIC set_property PACKAGE_PIN AM24 [get_ports "IIC_MAIN_SCL"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 154 PACKAGE_PIN AU24 [get_ports "PHY1_SGMII_OUT_P"]; set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "PHY1_SGMII_OUT_P"]; # SYSTEM CONTROLLER set_property PACKAGE_PIN BD21 [get_ports "SYSCTLR_GPIO_5"]; set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_5"]; set_property PACKAGE_PIN BA25 [get_ports "SYSCTLR_GPIO_6"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 155 BD22 [get_ports "FIREFLY_MODPRS_B"]; set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODPRS_B"]; set_property PACKAGE_PIN BC23 [get_ports "FIREFLY_MODSEL_B"]; set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODSEL_B"]; set_property PACKAGE_PIN BE24 [get_ports "FIREFLY_RESET_B"]; set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_RESET_B"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 156 LVCMOS12 [get_ports "GPIO_LED2"]; set_property PACKAGE_PIN BB32 [get_ports "GPIO_LED3"]; set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED3"]; set_property PACKAGE_PIN BF32 [get_ports "GPIO_LED4"]; set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED4"]; set_property PACKAGE_PIN AU37 [get_ports "GPIO_LED5"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 157 AU16 [get_ports "PMOD0_5_LS "]; set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS "]; set_property PACKAGE_PIN AT15 [get_ports "PMOD0_6_LS "]; set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS "]; set_property PACKAGE_PIN AT16 [get_ports "PMOD0_7_LS "]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 158 PACKAGE_PIN [get_ports "SM_FAN_TACH"]; set_property IOSTANDARD LVCMOS18 [get_ports "SM_FAN_TACH"]; # MAXIM CABLE set_property PACKAGE_PIN BF40 [get_ports "MAXIM_CABLE_LS_B"]; set_property IOSTANDARD LVCMOS12 [get_ports "MAXIM_CABLE_LS_B"]; # PMBUS set_property PACKAGE_PIN BB23 [get_ports "PMBUS_ALERT_FPGA"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 159 [get_ports "PMBUS_ALERT_FPGA"]; # VADJ PGOOD set_property PACKAGE_PIN AK35 [get_ports "VADJ_1V8_PGOOD_LS"]; set_property IOSTANDARD LVCMOS18 [get_ports "VADJ_1V8_PGOOD_LS"]; # FMC VADJ ON/OFF set_property PACKAGE_PIN AL29 [get_ports "FMC_VADJ_ON_LS"]; set_property IOSTANDARD LVCMOS18 [get_ports "FMC_VADJ_ON_LS"]; VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...
  • Page 160 This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the VCU118 board master answer record concerning the CE requirements for the PC Test Environment: VCU118 Evaluation Kit — Master Answer Record (AR 68268)

  • Page 161: Electromagnetic Compatibility

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. VCU118 Board User Guide Send Feedback UG1224 (v1.0) December 15, 2016 www.xilinx.com...

  • Page 162: Xilinx Resources

    Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the VCU118 board and its documentation is available on the following websites. VCU118 Evaluation Kit VCU118 Evaluation Kit –...
  • Page 163 13. Silicon Labs CP210x USB-to-UART Installation Guide (UG1033) 14. VCU118 System Controller Tutorial (XTP447) 15. VCU118 Software Install and Board Setup Tutorial (XTP449) 16. For additional documents associated with Xilinx devices, design tools, intellectual property, boards, and kits see the Xilinx documentation website.

  • Page 164: Please Read: Important Legal Notices

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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