User Pmod Gpio Header - Xilinx VCU110 User Manual

Table 1-49: VCU110 GPIO Connections to FPGA U1 (Cont'd)
FPGA Pin (U1)
L26
BD28
BC28
BE26
BF25
Notes:
1. LED signals are level-shifted from 3.3V to 1.2V with SN74AVC4T245 drivers U47 and U49.
2. Pushbutton SW7 is level-shifted from 1.2V to 1.8V with SN74AVCT245 driver U197 for the U111 Bank
501 connection.

User PMOD GPIO Header

[Figure 1-2, callout 29]
The VCU110 evaluation board supports one right-angle (FEMALE) PMOD GPIO receptacle
J52. The PMOD nets connected to J52 are accessed through level-shifter U41 (PMOD0). The
level-shifter is wired to XCVU190 FPGA U1 bank71.
Figure 1-22 shows the female GPIO PMOD header J52.
X-Ref Target - Figure 1-22
VCC1V2_FPGA
1 C72
0.1UF
2 25V
TXS0108E
GND
2
VCCA
PMOD0_0_LS
1
A1
PMOD0_1_LS
3
A2
PMOD0_2_LS
4
A3
PMOD0_3_LS
5
A4
PMOD0_4_LS
6
A5
PMOD0_5_LS
7
A6
PMOD0_6_LS
8
A7
PMOD0_7_LS
9
A8
10
OE
U41
Figure 1-22: PMOD Connectors J52 with Level-Shifter U41
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
(2)
GPIO_SW_C
4-Pole DIP Switch (Active-High)
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
UTIL_3V3
1 C71
0.1UF
2 25V
GND
19
VCCB
PMOD0_0
20
B1
PMOD0_1
18
B2
PMOD0_2
17
B3
PMOD0_3
16
B4
PMOD0_4
15
B5
PMOD0_5
14
B6
PMOD0_6
13
B7
PMOD0_7
12
B8
11
GND
TSSOP_20
GND
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Chapter 1: VCU110 Evaluation Board Features
I/O Standard
LVCMOS18
LVCMOS12 SW12.4
LVCMOS12 SW12.3
LVCMOS12 SW12.2
LVCMOS12 SW12.1
J52
PMOD0_0 1 2
PMOD0_1 3 4
PMOD0_2 5 6
PMOD0_3 7 8
9 10
11 12
HDR_2X6_F_RA
UTIL_3V3
GND
Send Feedback
GPIO
SW7.3
PMOD0_4
PMOD0_5
PMOD0_6
PMOD0_7
GND
94