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Table 1-36: VCU110 FPGA U1 GTH Quad 231 Connections
FPGA (U1)
FPGA (U1) Pin Name
MGTHTXP0_231
MGTHTXN0_231
MGTHRXP0_231
MGTHRXN0_231
MGTHTXP1_231
MGTHTXN1_231
MGTHRXP1_231
MGTHRXN1_231
MGTHTXP2_231
MGTHTXN2_231
MGTHRXP2_231
MGTHRXN2_231
MGTHTXP3_231
MGTHTXN3_231
MGTHRXP3_231
MGTHRXN3_231
MGTREFCLK0P_231
MGTREFCLK0N_231
MGTREFCLK1P_231
MGTREFCLK1N_231
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
G7
HMC_L0TX_4_P
G6
HMC_L0TX_4_N
G2
HMC_L0RX_4_C_P
G1
HMC_L0RX_4_C_N
F9
HMC_L0TX_11_P
F8
HMC_L0TX_11_N
F4
HMC_L0RX_11_C_P
F3
HMC_L0RX_11_C_N
G11
HMC_L0TX_6_P
G10
HMC_L0TX_6_N
G16
HMC_L0RX_6_C_P
G15
HMC_L0RX_6_C_N
F13
HMC_L0TX_2_P
F12
HMC_L0TX_2_N
E16
HMC_L0RX_2_C_P
E15
HMC_L0RX_2_C_N
N11
NA
N10
NA
M13
NA
M12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin Number
E20
L0RXP_4
E19
L0RXN_4
(2)
D25
L0TXP_4
(2)
D24
L0TXN_4
D29
L0RXP_11
D28
L0RXN_11
(2)
C26
L0TXP_11
(2)
C25
L0TXN_11
C22
L0RXP_6
C21
L0RXN_6
(2)
A20
L0TXP_6
(2)
A19
L0TXN_6
A16
L0RXP_2
A15
L0RXN_2
(2)
D17
L0TXP_2
(2)
D16
L0TXN_2
NA
NA
NA
NA
Connected
Name
Device
HMC
U160
NA
NA
NA
NA
NA
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