System Clock - Xilinx VCU110 User Manual

Table 1-12: VCU110 Clock Sources to XCVU190 FPGA U1 Connections (Cont'd)
Clock Source
Reference
Schematic Net Name
Designator
and Pin
J34.1
J35.1
Notes:
1. Series resistor coupled.
2. Series capacitor coupled.
3. MGT connections I/O standard not applicable.
For more details on the Silicon Labs SI5335A, SI570, SI53340 and SI5328C devices, see
[Ref 26].
UltraScale FPGA clocking information may be found in the UltraScale Architecture Clocking
Resources User Guide (UG572)

System Clock

[Figure 1-2, callout 10]
The system clock source is a Silicon Labs SI5335A Quad clock generator/buffer (U122). The
system clock (SYSCLK_300_P/N) is a LVDS 300 MHz clock sourced from the CLK0A output
pair of U122. The SYSCLK_300_P/N pair is connected to XCVU190 FPGA U1 Bank 71 global
clock (GC) pins J24 and H24, respectively.
• Clock generator: Silicon Labs SI5335A-B03426-GM (CLK0A 300 MHz)
• Low phase jitter of 0.7 ps RMS
• LVDS differential output
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
USER_SMA_CLOCK_P
USER_SMA_CLOCK_N
[Ref 4].
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
Connected
I/O Standard
Pin
LVDS AY27
LVDS AY28
Connection or FPGA
(U1) Bank
67
39
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