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Table 1-6: RLD3 Memory U173 18-bit I/F to FPGA U1 Bank 72 (Cont'd)
FPGA (U1) Pin
A18
B20
G20
B18
C20
D20
D19
E21
F19
B21
A21
C19
C18
K17
J17
N18
M18
J15
The VCU110 RLD3 36-bit and 18-bit memory component interfaces adhere to the
constraints guidelines documented in the RLD3 Design Guidelines section of LogiCORE IP
UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150)
[Ref 3]
for Vivado Design Suite. The VCU110 RLD3 memory component interface is a 40Ω
impedance implementation.
For more details about the Micron RLD3 component memory, see the Micron
MT44K16M36RB-093E/ MT44K32M18RB-093E data sheet
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Chapter 1:
Schematic Net Name
RLD3_18B_BA1
RLD3_18B_BA2
RLD3_18B_BA3
RLD3_18B_WE_B
RLD3_18B_REF_B
RLD3_18B_CK_P
RLD3_18B_CK_N
RLD3_18B_RESET_B
RLD3_18B_CS_B
RLD3_18B_DK0_P
RLD3_18B_DK0_N
RLD3_18B_DK1_P
RLD3_18B_DK1_N
RLD3_18B_QK0_P
RLD3_18B_QK0_N
RLD3_18B_QK1_P
RLD3_18B_QK1_N
RLD3_18B_QVLD0
www.xilinx.com
VCU110 Evaluation Board Features
I/O Standard
SSTL12
SSTL12
SSTL12
SSTL12
SSTL12
DIFF_SSTL12
DIFF_SSTL12
SSTL12
SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
DIFF_SSTL12
SSTL12
[Ref
22].
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22
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