Interlaken Connector - Xilinx VCU110 User Manual

Interlaken Connector

[Figure 1-2, callout 42]
The VCU110 board provides an FCI Interlaken connector at J121. Five FPGA U1 GTY Quads
(129-133) implement twenty transmit/receive differential pair channels. The Interlaken
connector DATA, CLK and SYNC control signals are connected to FPGA U1 Bank 65.
The Interlaken J121 to FPGA U1 connections are detailed in
Table 1-54: VCU110 Interlaken Connector J121 Connections
Interlaken Interlaken
J121 Pin
Name
TX0_P
TX0_N
RX0_P
RX0_N
TX1_P
TX1_N
RX1_P
RX1_N
TX2_P
TX2_N
RX2_P
RX2_N
TX3_P
TX3_N
RX3_P
RX3_N
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J121 Pin Schematic Net Name
Number
A2 ILKN_TX0_P
A3 ILKN_TX0_N
B2 ILKN_RX0_C_P
B3 ILKN_RX0_C_N
C2 ILKN_TX1_P
C3 ILKN_TX1_N
D2 ILKN_RX1_C_P
D3 ILKN_RX1_C_N
A5 ILKN_TX2_P
A6 ILKN_TX2_N
B5 ILKN_RX2_C_P
B6 ILKN_RX2_C_N
C5 ILKN_TX3_P
C6 ILKN_TX3_N
D5 ILKN_RX3_C_P
D6 ILKN_RX3_C_N
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Chapter 1: VCU110 Evaluation Board Features
Table
FPGA FPGA (U1) Pin
(2)
(U1) Pin Name
R40 MGTYTXP0_129
R41 MGTYTXN0_129
(1)
R45 MGTYRXP0_129
(1)
R46 MGTYRXN0_129
P38 MGTYTXP1_129
P39 MGTYTXN1_129
(1)
P43 MGTYRXP1_129
(1)
P44 MGTYRXN1_129
N40 MGTYTXP2_129
N41 MGTYTXN2_129
(1)
N45 MGTYRXP2_129
(1)
N46 MGTYRXN2_129
M38 MGTYTXP3_129
M39 MGTYTXN3_129
(1)
M43 MGTYRXP3_129
(1)
M44 MGTYRXN3_129
1-54.
FPGA U1 Bank
GTY Quad 129
104
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