Xilinx VC709 User Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Motherboard
  5. VC709
  6. User manual

Xilinx VC709 User Manual

For the virtex-7 fpga
Hide thumbs Also See for VC709:
Table of Contents

Advertisement

Quick Links

Download this manual
VC709 Evaluation
Board for the
Virtex-7 FPGA
User Guide
UG887 (v1.2.1) March 11, 2014

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the VC709 and is the answer not in the manual?

Questions and answers

Related Manuals for Xilinx VC709

Summary of Contents for Xilinx VC709

  • Page 1 VC709 Evaluation Board for the Virtex-7 FPGA User Guide UG887 (v1.2.1) March 11, 2014...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    VC709 Board Features ........
  • Page 4 ..............100 www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 5: Chapter 1: Vc709 Evaluation Board Features

    Chapter 1 VC709 Evaluation Board Features Overview The VC709 evaluation board for the Virtex®-7 FPGA provides a hardware environment for developing and evaluating designs targeting the Virtex-7 XC7VX690T-2FFG1761C FPGA. The VC709 board provides features common to many embedded processing systems, including dual DDR3 small outline dual-inline memory module (SODIMM) memories, an 8-lane PCI Express®...
  • Page 6 USB JTAG (Digilent) configuration port The VC709 board block diagram is shown in Figure 1-1. Caution! The VC709 board can be damaged by electrostatic discharge (ESD). Follow standard ESD prevention measures when handling the board. www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 7: Feature Descriptions

    C Bus Switch Flash Addr Connector UG887_c1_01_012113 Figure 1-1: VC709 Board Block Diagram Feature Descriptions Figure 1-2 shows the VC709 board. Each numbered feature that is referenced in Figure 1-2 is described in Table 1-1 and following sections. Note: The image in...
  • Page 8 Chapter 1: VC709 Evaluation Board Features X-Ref Target - Figure 1-2 Round callout references a component Square callout references a component on the front side of the board. on the back side of the board. UG887_c1_02_051013 Figure 1-2: VC709 Board Component Locations...

  • Page 9: Virtex-7 Xc7Vx690T-2Ffg1761C Fpga

    For further information on Virtex-7 FPGAs, see 7 Series FPGAs Overview (DS180) [Ref FPGA Configuration The VC709 board supports two of the five 7 series FPGA configuration modes: • Master BPI using the onboard linear BPI flash memory VC709 Evaluation Board www.xilinx.com...
  • Page 10 There are 17 I/O banks available on the Virtex-7 device. Fourteen I/O banks are available on the VC709 board, and banks 12, 16, and 18 are not used. The voltages applied to the FPGA I/O banks used by the VC709 board are listed in Table 1-3.

  • Page 11: Dual Ddr3 Memory Sodimms

    Table 1-5. Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Number DDR3_A_A0 DDR3_A_A1 DDR3_A_A2 DDR3_A_A3 DDR3_A_A4 DDR3_A_A5 DDR3_A_A6 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 12 Chapter 1: VC709 Evaluation Board Features Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA (Cont’d) SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Number DDR3_A_A7 DDR3_A_A8 DDR3_A_A9 DDR3_A_A10 A10/AP DDR3_A_A11 DDR3_A_A12 A12_BC_N DDR3_A_A13 DDR3_A_A14 DDR3_A_A15...
  • Page 13 DQ36 DDR3_A_D37 DQ37 DDR3_A_D38 DQ38 DDR3_A_D39 DQ39 DDR3_A_D40 DQ40 DDR3_A_D41 DQ41 DDR3_A_D42 DQ42 DDR3_A_D43 DQ43 DDR3_A_D44 DQ44 DDR3_A_D45 DQ45 DDR3_A_D46 DQ46 DDR3_A_D47 DQ47 DDR3_A_D48 DQ48 DDR3_A_D49 DQ49 DDR3_A_D50 DQ50 DDR3_A_D51 DQ51 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 14 Chapter 1: VC709 Evaluation Board Features Table 1-4: DDR3 SODIMM Socket J1 Connections to the FPGA (Cont’d) SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Number DDR3_A_D52 DQ52 DDR3_A_D53 DQ53 DDR3_A_D54 DQ54 DDR3_A_D55 DQ55 DDR3_A_D56 DQ56 DDR3_A_D57...
  • Page 15 Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Name AN19 DDR3_B_A0 AR19 DDR3_B_A1 AP20 DDR3_B_A2 AP17 DDR3_B_A3 AP18 DDR3_B_A4 AJ18 DDR3_B_A5 AN16 DDR3_B_A6 AM16 DDR3_B_A7 AK18 DDR3_B_A8 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 16 Chapter 1: VC709 Evaluation Board Features Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont’d) SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Name AK19 DDR3_B_A9 AM17 DDR3_B_A10 A10/AP AM18 DDR3_B_A11 AL17 DDR3_B_A12 A12_BC_N AK17...
  • Page 17 DQ43 AV13 DDR3_B_D44 DQ44 AW13 DDR3_B_D45 DQ45 AT15 DDR3_B_D46 DQ46 AR15 DDR3_B_D47 DQ47 AL15 DDR3_B_D48 DQ48 AJ15 DDR3_B_D49 DQ49 AK14 DDR3_B_D50 DQ50 AJ12 DDR3_B_D51 DQ51 AJ16 DDR3_B_D52 DQ52 AL16 DDR3_B_D53 DQ53 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 18 Chapter 1: VC709 Evaluation Board Features Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont’d) SODIMM Memory J3 XCVX690T (U1) Pin Net Name Pin Number Pin Name AJ13 DDR3_B_D54 DQ54 AK13 DDR3_B_D55 DQ55 AR14 DDR3_B_D56 DQ56 AT14 DDR3_B_D57...

  • Page 19: Linear Bpi Flash Memory

    RESET_B AU16 DDR3_B_TEMP_EVENT_B EVENT_B The VC709 DDR3 SODIMM interfaces adhere to the constraints guidelines documented in the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions User Guide (UG586) [Ref 3]. The VC709 DDR3 SODIMM interfaces are 40Ω impedance implementations.
  • Page 20 Chapter 1: VC709 Evaluation Board Features fastest configuration method uses the external 80 MHz oscillator connected to the FPGA EMCCLK pin. Multiple bitstreams can be stored in the linear BPI flash. The two most significant address bits (A25, A24) of the flash memory are connected to DIP switch SW11 positions 1 and 2 respectively, and to the RS1 and RS0 pins of the FPGA.
  • Page 21 The configuration section of 7 Series FPGAs Configuration User Guide (UG470) [Ref 2] provides details on the Master BPI configuration mode. Figure 1-4 shows the linear BPI flash memory on the VC709 board. For more details, see the Micron Semiconductor PC28F00AG18FE data sheet. VC709 Evaluation Board www.xilinx.com...
  • Page 22 Chapter 1: VC709 Evaluation Board Features X-Ref Target - Figure 1-4 PC28F00AG18FE 64-Pin BGA (8 x 10 mm) FLASH_D0_R FLASH_A0 FLASH_D1_R FLASH_A1 FLASH_D2_R FLASH_A2 FLASH_D3_R FLASH_A3 FLASH_D4_R FLASH_A4 FLASH_D5_R FLASH_A5 FLASH_D6_R FLASH_A6 FLASH_D7_R FLASH_A7 FLASH_D8_R FLASH_A8 FLASH_A9 FLASH_D9_R FLASH_D10_R FLASH_A10...

  • Page 23: Usb Jtag

    UG887_c1_05_100912 Figure 1-5: JTAG Chain Block Diagram When an FMC mezzanine card is attached to the VC709 HPC connector J35, it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switch U27. The SPST switch is in a normally closed state and transitions to an open state when an FMC mezzanine card is attached.
  • Page 24 Chapter 1: VC709 Evaluation Board Features The JTAG circuit details are shown in Figure 1-6. X-Ref Target - Figure 1-6 UG855_c1_06_011013 Figure 1-6: JTAG Circuit www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 25: Clock Generation

    Feature Descriptions Clock Generation The VC709 board provides six clock sources for the FPGA. Table 1-7 lists the source devices for each clock. Table 1-7: VC709 Board Clock Sources Clock Clock Name Description Source SiT9102 2.5V LVDS 200 MHz fixed frequency oscillator (Si Time)
  • Page 26 [Figure 1-2, callout 5] The VC709 board has an LVDS 200 MHz oscillator (U51) soldered onto the back side of the board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins H19 and G18 respectively.
  • Page 27 On power-up, the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I C interface. Power cycling the VC709 board reverts the user clock to its default frequency of 156.250 MHz. •...
  • Page 28 [Figure 1-2, callout 8] The VC709 board includes a pair of SMA connectors for a GTH clock wired to GTH Quad bank 113. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to FPGA U1 pins AK8 and AK7 respectively.
  • Page 29 [Figure 1-2, callout 9] The VC709 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the board. FPGA user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin AW32 and REC_CLOCK_C_N, FPGA U1 pin AW33) for jitter attenuation.

  • Page 30: Memory Clock (Sysclk_233_P And Sysclk_233_N)

    [Figure 1-2, callout 27] The VC709 board has a LVDS 233.3333 MHz oscillator (U13) soldered onto the back side of the board and wired to an FPGA MRCC clock input on bank 32. This 233.3333 MHz signal pair is named SYSCLK_233_P and SYSCLK_233_N. The P and N signals are connected to FPGA U1 pins AY18 and AY17 respectively.

  • Page 31: Fpga Emcc Clock

    There is no The VC709 board has a LVCMOS 80 MHz oscillator (U40) soldered onto the board and wired to the FPGA EMCCLK clock input pin AP37 on bank 14. This 80 MHz single-ended signal is named FPGA_EMCCLK.

  • Page 32: Gth Transceivers

    The GTH transceivers in 7 series FPGAs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTH Quad of interest. There are six GTH Quads on the VC709 board with connectivity as shown here: •...
  • Page 33 Si5324 jitter attenuator MGTREFCLK1 SMA_MGT_REFCLK MGT_BANK_114 GTHE2_CHANNEL_X1Y19 PCIe4 GTHE2_CHANNEL_X1Y18 PCIe5 GTHE2_CHANNEL_X1Y17 PCIe6 GTHE2_CHANNEL_X1Y16 PCIe7 MGTREFCLK0 MGTREFCLK1 MGT_BANK_115 GTHE2_CHANNEL_X1Y23 PCIe0 GTHE2_CHANNEL_X1Y22 PCIe1 GTHE2_CHANNEL_X1Y21 PCIe2 GTHE2_CHANNEL_X1Y20 PCIe3 MGTREFCLK0 MGTREFCLK1 PCIe_CLK MGT_BANK_117 GTHE2_CHANNEL_X1Y31 GTHE2_CHANNEL_X1Y30 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...

  • Page 34: Pci Express Endpoint Connectivity

    85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTH transceivers are used for multi-gigabit per second serial interfaces. The XC7VX690T-2FFG1761C FPGA (-2 speed grade) included with the VC709 board supports up to Gen3 x8.
  • Page 35 Integrated Endpoint block GTHE2_CHANNEL_X1Y21 PCIE_RX2_N PETn2 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y20 PCIE_RX3_P PETp3 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y20 PCIE_RX3_N PETn3 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y19 PCIE_RX4_P PETp4 receive pair VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 36 Chapter 1: VC709 Evaluation Board Features Table 1-10: PCIe Edge Connector Connections (Cont’d) PCIe Edge Connector (P1) Net Name FPGA (U1) Pin Function FFG1761 Placement Name Integrated Endpoint block GTHE2_CHANNEL_X1Y19 PCIE_RX4_N PETn4 receive pair Integrated Endpoint block GTHE2_CHANNEL_X1Y18 PCIE_RX5_P PETp5...
  • Page 37 PCIE_RX3_P PETp3 GTHE2_CHANNEL_X1Y20 MGTXRXN0_115_AC5 PCIE_RX3_N PETn3 GTHE2_CHANNEL_X1Y20 MGTXTXP1_115_AC2 PCIE_TX2_P PERp2 GTHE2_CHANNEL_X1Y21 MGTXTXN1_115_AC1 PCIE_TX2_N PERn2 GTHE2_CHANNEL_X1Y21 MGTXRXP1_115_AB4 PCIE_RX2_P PETp2 GTHE2_CHANNEL_X1Y21 MGTXRXN1_115_AB3 PCIE_RX2_N PETn2 GTHE2_CHANNEL_X1Y21 MGTXTXP2_115_AA2 PCIE_TX1_P PERp1 GTHE2_CHANNEL_X1Y22 MGTXTXN2_115_AA1 PCIE_TX1_N PERn1 GTHE2_CHANNEL_X1Y22 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 38 Chapter 1: VC709 Evaluation Board Features Table 1-11: GTH Quad 115 PCIe Edge Connector Connections (Cont’d) PCIe Edge Connector FPGA (P1) Quad 115 Pin Name Net Name FFG1761 Placement (U1) Pin Pin Name MGTXRXP2_115_AA6 PCIE_RX1_P PETp1 GTHE2_CHANNEL_X1Y22 MGTXRXN2_115_AA5 PCIE_RX1_N PETn1...

  • Page 39: Sfp/Sfp+ Module Connectors

    [Ref SFP/SFP+ Module Connectors [Figure 1-2, callout 12] The VC709 board supports four small form-factor pluggable (SFP+) connector and cage assemblies P2–P5 that accept SFP or SFP+ modules. Figure 1-16 shows an example of the SFP+ module connector circuitry replicated for each module.
  • Page 40 Chapter 1: VC709 Evaluation Board Features X-Ref Target - Figure 1-16 74754-0101 VCC3V3 4.7UH 74441-0010 3.0A VCC3V3 SFP1_VCCR 12_SFP1_RX_N VCCR RD_N SFP1_VCCT 13_SFP1_RX_P VCCT RD_P 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 18_SFP1_TX_P 1/10W 1/10W 1/10W 1/10W 1/10W 1/10W VEER_1 TD_P...
  • Page 41 SFP+ Module 1 (P3) SFP1_TX_FAULT TX_FAULT AB42 SFP1_MOD_DETECT MOD_ABS SFP1_RS0 SFP1_RS1 SFP1_LOS AB41 SFP1_TX_DISABLE TX_DISABLE SFP+ Module 2 (P2) AA39 SFP2_TX_FAULT TX_FAULT AA42 SFP2_MOD_DETECT MOD_ABS AB38 SFP2_RS0 AB39 SFP2_RS1 AA40 SFP2_LOS SFP2_TX_DISABLE TX_DISABLE VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...

  • Page 42: Usb-To-Uart Bridge

    USB port. The USB cable is supplied in the VC709 evaluation kit (type-A end to host computer, type mini-B end to VC709 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC709 board.

  • Page 43: I 2 C Bus

    The four SFP+ connectors SFP1 (P3), SFP2 (P2), SFP3 (P4), and SFP4 (P5) are addressed through a secondary PCA9546A 1-to-4 channel I C bus switch (U14). The VC709 board I bus topology is shown in Figure 1-17.
  • Page 44 Chapter 1: VC709 Evaluation Board Features X-Ref Target - Figure 1-17 PCA9548 1 2 C 1-to-8 Bus Switch CH0 - USER_CLK_SDL/SCL CH1 - FMC1_HPC_IIC_SDA/SCL FPGA Bank 15 CH2 - Not used (2.5V) CH3 - EEPROM_IIC_SDA/SCL IIC_SDA/SCL_MAIN CH4 - SFP_IIC_SDA/SCL CH5 - Not used...

  • Page 45: Status Leds

    DDR3 SODIMMs VTT power good User I/O [Figure 1-2, callout 16, 18] The VC709 board provides the following user and general purpose I/O capabilities: • Eight user LEDs (callout 16) • GPIO_LED_[7-0]: DS9, DS8, DS7, DS6, DS5, DS4, DS3, DS2 •...

  • Page 46: User Leds

    Chapter 1: VC709 Evaluation Board Features User LEDs Figure 1-18 shows the user LED circuits. X-Ref Target - Figure 1-18 GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 GPIO_LED_4 GPIO_LED_5 GPIO_LED_6 GPIO_LED_7 R154 R153 R152 R151 R150 R149 R148 R147 49.9 49.9 49.9 49.9 49.9...
  • Page 47 Pushbutton Pushbutton TL3301EF100QG TL3301EF100QG TL3301EF100QG GPIO_SW_W GPIO_SW_C GPIO_SW_E 4.7K 4.7K 4.7K 1/10W 1/10W 1/10W VCC1V8 VCC1V8 Pushbutton Pushbutton TL3301EF100QG TL3301EF100QG CPU_RESET GPIO_SW_S 4.7K 4.7K 1/10W 1/10W UG887_c1_18_090612 Figure 1-19: User Pushbuttons VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 48 Chapter 1: VC709 Evaluation Board Features Figure 1-20 shows the GPIO DIP switch circuit. X-Ref Target - Figure 1-20 VCC1V8 SDA08H1SBD GPIO_DIP_SW0 GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 GPIO_DIP_SW4 GPIO_DIP_SW5 GPIO_DIP_SW6 GPIO_DIP_SW7 4.7K 4.7K 4.7K 4.7K 1/10W 1/10W 1/10W 1/10W 4.7K 4.7K 4.7K 4.7K...

  • Page 49: Switches

    AV40 CPU_RESET SW8.3 Switches [Figure 1-2, callout 19, 20, and 21] The VC709 board includes a power and a configuration switch: • FPGA_PROG_B , active-Low pushbutton switch SW9 (callout 19) • Configuration mode DIP switch SW11 (callout 20) • Power on/off slide switch SW12 (callout 21)
  • Page 50 [Figure 1-2, callout 21] The VC709 board power switch is SW12. Sliding the switch actuator from the Off to On position applies 12V power from J18, a 6-pin mini-fit connector. Green LED DS16 illuminates when the VC709 board 12V power is on. See Power Management, page 56 details on the onboard power system.

  • Page 51: Vita 57.1 Fmc1 Hpc Connector (Partially Populated)

    2 GTH clocks • 4 differential clocks • 159 ground and 15 power connections The VC709 board FMC1 HPC connector J35 implements a subset of the maximum signal and clock connectivity capabilities: • 80 differential user-defined pairs: • 34 LA pairs (LA00-LA33) •...
  • Page 52 • 2 differential clocks The FMC1 HPC signals are distributed across GTH Quads 117, 118, and 119. The VC709 board VADJ voltage for the FMC1 HPC (J35) connector is fixed at 1.8V. Signaling speed ratings: • Single-ended: 9 GHz (18 Gb/s) •...
  • Page 53 FMC1_HPC_LA14_N FMC1_HPC_LA13_P FMC1_HPC_LA18_CC_P FMC1_HPC_LA13_N FMC1_HPC_LA18_CC_N FMC1_HPC_LA17_CC_P FMC1_HPC_LA27_P FMC1_HPC_LA17_CC_N FMC1_HPC_LA27_N FMC1_HPC_LA23_P FMC1_HPC_IIC_SCL U52.4 FMC1_HPC_LA23_N FMC1_HPC_IIC_SDA U52.3 FMC1_HPC_LA26_P FMC1_HPC_LA26_N VCC12_P FMC1_HPC_TCK_BUF U19.14 VCC12_P FMC1_TDI_BUF U19.18 VCC3V3 FMC1_TDO_FPGA_TDI VCC3V3 FMC1_HPC_TMS_BUF U19.17 VCC3V3 VCC3V3 VCC3V3 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 54 Chapter 1: VC709 Evaluation Board Features Table 1-20: VITA 57.1 FMC HPC J35 Connections to FPGA U1 (Cont’d) J35 FMC J64 FMC U1 FPGA Schematic Net Name U1 FPGA Pin Schematic Net Name HPC Pin HPC Pin FMC1_HPC_HA01_CC_P FMC1_HPC_PG_M2C AN34...
  • Page 55 FMC1_HPC_LA25_N FMC1_HPC_LA21_N FMC1_HPC_LA29_P FMC1_HPC_LA24_P FMC1_HPC_LA29_N FMC1_HPC_LA24_N FMC1_HPC_LA31_P FMC1_HPC_LA28_P FMC1_HPC_LA31_N FMC1_HPC_LA28_N FMC1_HPC_LA33_P FMC1_HPC_LA30_P FMC1_HPC_LA33_N FMC1_HPC_LA30_N VCC1V8 FMC1_HPC_LA32_P FMC1_HPC_LA32_N VCC1V8 FMC1_HPC_HA03_P FMC1_HPC_HA03_N FMC1_HPC_HA02_P FMC1_HPC_HA07_P FMC1_HPC_HA02_N FMC1_HPC_HA07_N FMC1_HPC_HA06_P FMC1_HPC_HA11_P FMC1_HPC_HA06_N FMC1_HPC_HA11_N FMC1_HPC_HA10_P FMC1_HPC_HA14_P FMC1_HPC_HA10_N VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...

  • Page 56: Power Management

    2. FMC1_VIO_B_M2C is a variable voltage but it cannot exceed the fixed VADJ 1.8V value. Power Management [Figure 1-2, callout 26] The VC709 board power distribution diagram is shown in Figure 1-25. The PCB layout and power system have been designed to meet the recommended criteria...
  • Page 57 VCC3V3 0.75V at 3A Max TPS51200 U23 UG887_c1_24_012113 Figure 1-25: Onboard Power Regulators The VC709 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instrument digital power to supply the core and auxiliary VC709 Evaluation Board www.xilinx.com...
  • Page 58 Chapter 1: VC709 Evaluation Board Features voltages listed in Table 1-21. U10 is an ADP123 linear regulator from Analog Devices. Table 1-21: Onboard Power System Devices Reference Power Rail Power Rail Schematic Device Type Description Designator Net Name Voltage Page...

  • Page 59: Fmc_Vadj Voltage

    54) are wired to the same PMBus. The PMBus connector, J5, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the Texas Instruments Xilinx USB website and the associated TI Fusion Digital Power Designer GUI also downloadable from Texas Instruments fusion tools.
  • Page 60 Chapter 1: VC709 Evaluation Board Features Table 1-23 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 53 (U43). Table 1-23: Power Rail Specifications for UCD9248 PMBus Controller at Address 53...

  • Page 61: Xadc Analog-To-Digital Converter

    Texas Instruments fusion tools Note: It has been noted that power modules on the VC709 evaluation board that operate at moderate to high current levels (due to a customer design) might generate substantial heat that can result in unexpected power module shutdowns from over-temperature conditions. This then turns off Virtex-7 VC709 Evaluation Kit Master the FPGA on the development board.
  • Page 62 100Ω UG887_c1_25_011013 Figure 1-26: XADC Block Diagram The VC709 board supports both the internal FPGA sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, , and V are available. The VC709 board V...

  • Page 63: Configuration Options

    19, 20, 17, 18 shared with other functions because they are required to support 3-state operation. Configuration Options The FPGA on the VC709 board can be configured by the following methods: • Master BPI (uses the linear BPI flash). •...
  • Page 64 Chapter 1: VC709 Evaluation Board Features Table 1-26: Mode Switch SW11 Settings Mode Pins Configuration Mode (M2, M1, M0) Master BPI JTAG Figure 1-28 shows mode switch SW13. X-Ref Target - Figure 1-28 VCC2V5 R401 R402 220Ω 220Ω 0.1 W 0.1 W...
  • Page 65 (VCCO = 1.8V) A[26:25] FLASH_A[25:0] A[26:1] A[23:16] A[15:0] D[15:0] D[15:0] Bank 14 (VCCO = 1.8V) CE_B FCS_B WAIT RDWR_B (VCC, VCCQ, 1.8V) Oscillator EMCCLK 80 MHz UG887_c1_28_052213 Figure 1-29: VC709 Board Configuration Circuit VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 66 Chapter 1: VC709 Evaluation Board Features www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 67: Gpio Dip Switch Sw2

    2 3 4 5 6 7 8 OFF Position = 0 UG887_aA_01_083012 Figure A-1: SW2 Default Settings Table A-1: SW2 Default Switch Settings Position Function Default GPIO_DIP_SW0 GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 GPIO_DIP_SW4 GPIO_DIP_SW5 GPIO_DIP_SW6 GPIO_DIP_SW7 VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...

  • Page 68: Configuration Dip Switch Sw11

    XADC REF3012 U35 VIN select PCIe bus width select header TI controller U42 Addr 52 Reset jumper None TI controller U43 Addr 53 Reset jumper None TI controller U64 Addr 54 Reset jumper None www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 69: Appendix B: Vita 57.1 Fmc Connector Pinouts

    DP6_C2M_P HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N 12P0V DP6_C2M_N HB17_N_CC LA32_N HB20_N 3P3V DP5_C2M_P VIO_B_M2C VADJ VADJ 3P3V DP5_C2M_N VIO_B_M2C VADJ VADJ 3P3V RES0 UG887_aB_01_083012 Figure B-1: FMC1 HPC Connector Pinout VC709 Evaluation Board www.xilinx.com UG887 (v1.2.1) March 11, 2014...
  • Page 70 Appendix B: VITA 57.1 FMC Connector Pinouts www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 71: Appendix C: Master Xdc Listing

    The VC709 board master Xilinx design constraints (XDC) file template provides for designs targeting the VC709 board. Net names in the constraints listed in this appendix correlate with net names on the latest VC709 board schematic. Users must identify the appropriate pins and replace the net names listed here with net names in the user RTL.
  • Page 72 PACKAGE_PIN AK34 [get_ports USER_CLOCK_P] set_property IOSTANDARD LVDS [get_ports USER_CLOCK_P] set_property PACKAGE_PIN AL34 [get_ports USER_CLOCK_N] set_property IOSTANDARD LVDS [get_ports USER_CLOCK_N] set_property PACKAGE_PIN AJ32 [get_ports USER_SMA_CLOCK_P] set_property IOSTANDARD LVDS [get_ports USER_SMA_CLOCK_P] set_property PACKAGE_PIN AK32 [get_ports USER_SMA_CLOCK_N] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 73 VC709 Board XDC Listing set_property IOSTANDARD LVDS [get_ports USER_SMA_CLOCK_N] set_property PACKAGE_PIN AL32 [get_ports FMC_C2M_PG_LS] set_property IOSTANDARD LVCMOS18 [get_ports FMC_C2M_PG_LS] set_property PACKAGE_PIN AM34 [get_ports FLASH_WAIT] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_WAIT] set_property PACKAGE_PIN AN34 [get_ports FMC1_HPC_PG_M2C_LS] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_PG_M2C_LS] set_property PACKAGE_PIN AM31 [get_ports FMC1_HPC_PRSNT_M2C_B_LS]...
  • Page 74 PACKAGE_PIN AV41 [get_ports FLASH_A16] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A16] set_property PACKAGE_PIN BA41 [get_ports FLASH_OE_B] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_OE_B] set_property PACKAGE_PIN BB41 [get_ports FLASH_FWE_B] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_FWE_B] set_property PACKAGE_PIN AW41 [get_ports FLASH_A25] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 75 VC709 Board XDC Listing set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A25] set_property PACKAGE_PIN AW42 [get_ports FLASH_A24] set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A24] set_property PACKAGE_PIN Y38 [get_ports SFP1_TX_FAULT_LS] set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_FAULT_LS] set_property PACKAGE_PIN AB41 [get_ports SFP1_TX_DISABLE_LS_B] set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_DISABLE_LS_B] set_property PACKAGE_PIN AB42 [get_ports SFP1_MOD_DETECT_LS]...
  • Page 76 PACKAGE_PIN N38 [get_ports FMC1_HPC_LA10_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA10_P] set_property PACKAGE_PIN M39 [get_ports FMC1_HPC_LA10_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA10_N] set_property PACKAGE_PIN R40 [get_ports FMC1_HPC_LA12_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA12_P] set_property PACKAGE_PIN P40 [get_ports FMC1_HPC_LA12_N] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 77 VC709 Board XDC Listing set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA12_N] set_property PACKAGE_PIN N39 [get_ports FMC1_HPC_LA14_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA14_P] set_property PACKAGE_PIN N40 [get_ports FMC1_HPC_LA14_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_LA14_N] set_property PACKAGE_PIN AJ16 [get_ports DDR3_B_D52] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D52] set_property PACKAGE_PIN AJ15 [get_ports DDR3_B_D49]...
  • Page 78 PACKAGE_PIN AN16 [get_ports DDR3_B_A6] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A6] set_property PACKAGE_PIN AJ18 [get_ports DDR3_B_A5] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A5] set_property PACKAGE_PIN AP18 [get_ports DDR3_B_A4] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A4] set_property PACKAGE_PIN AP17 [get_ports DDR3_B_A3] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 79 VC709 Board XDC Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A3] set_property PACKAGE_PIN AP20 [get_ports DDR3_B_A2] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A2] set_property PACKAGE_PIN AR19 [get_ports DDR3_B_A1] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A1] set_property PACKAGE_PIN AN19 [get_ports DDR3_B_A0] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A0] set_property PACKAGE_PIN AN18 [get_ports DDR3_B_BA2]...
  • Page 80 PACKAGE_PIN AU24 [get_ports DDR3_B_DM2] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM2] set_property PACKAGE_PIN AY23 [get_ports DDR3_B_D26] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D26] set_property PACKAGE_PIN AY25 [get_ports DDR3_B_D28] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D28] set_property PACKAGE_PIN BA25 [get_ports DDR3_B_D29] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 81 VC709 Board XDC Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D29] set_property PACKAGE_PIN BA22 [get_ports DDR3_B_DQS3_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS3_P] set_property PACKAGE_PIN BB22 [get_ports DDR3_B_DQS3_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS3_N] set_property PACKAGE_PIN AY24 [get_ports DDR3_B_D27] set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D27] set_property PACKAGE_PIN BA24 [get_ports DDR3_B_D25]...
  • Page 82 PACKAGE_PIN B38 [get_ports FMC1_HPC_HA12_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA12_N] set_property PACKAGE_PIN E32 [get_ports FMC1_HPC_HA09_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA09_P] set_property PACKAGE_PIN D32 [get_ports FMC1_HPC_HA09_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA09_N] set_property PACKAGE_PIN B32 [get_ports FMC1_HPC_HA19_P] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 83 VC709 Board XDC Listing set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA19_P] set_property PACKAGE_PIN B33 [get_ports FMC1_HPC_HA19_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA19_N] set_property PACKAGE_PIN E33 [get_ports FMC1_HPC_HA02_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA02_P] set_property PACKAGE_PIN D33 [get_ports FMC1_HPC_HA02_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HA02_N] set_property PACKAGE_PIN C33 [get_ports FMC1_HPC_HA15_P]...
  • Page 84 PACKAGE_PIN J25 [get_ports FMC1_HPC_HB00_CC_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB00_CC_P] set_property PACKAGE_PIN J26 [get_ports FMC1_HPC_HB00_CC_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB00_CC_N] set_property PACKAGE_PIN M24 [get_ports FMC1_HPC_HB17_CC_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB17_CC_P] set_property PACKAGE_PIN L24 [get_ports FMC1_HPC_HB17_CC_N] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 85 VC709 Board XDC Listing set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB17_CC_N] set_property PACKAGE_PIN K23 [get_ports FMC1_HPC_HB06_CC_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB06_CC_P] set_property PACKAGE_PIN J23 [get_ports FMC1_HPC_HB06_CC_N] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB06_CC_N] set_property PACKAGE_PIN M22 [get_ports FMC1_HPC_HB10_P] set_property IOSTANDARD LVCMOS18 [get_ports FMC1_HPC_HB10_P] set_property PACKAGE_PIN L22 [get_ports FMC1_HPC_HB10_N]...
  • Page 86 PACKAGE_PIN E28 [get_ports DDR3_A_DQS7_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS7_N] set_property PACKAGE_PIN F29 [get_ports DDR3_A_D57] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D57] set_property PACKAGE_PIN E29 [get_ports DDR3_A_D61] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D61] set_property PACKAGE_PIN F26 [get_ports DDR3_A_D62] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 87 VC709 Board XDC Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D62] set_property PACKAGE_PIN F27 [get_ports DDR3_A_D59] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D59] set_property PACKAGE_PIN F30 [get_ports DDR3_A_D58] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D58] set_property PACKAGE_PIN F31 [get_ports DDR3_A_DM7] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM7] set_property PACKAGE_PIN C19 [get_ports DDR3_A_A9]...
  • Page 88 PACKAGE_PIN G12 [get_ports DDR3_A_D21] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D21] set_property PACKAGE_PIN F12 [get_ports DDR3_A_DM2] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM2] set_property PACKAGE_PIN F15 [get_ports DDR3_A_D18] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D18] set_property PACKAGE_PIN F14 [get_ports DDR3_A_D22] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 89 VC709 Board XDC Listing set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D22] set_property PACKAGE_PIN G14 [get_ports DDR3_A_D23] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D23] set_property PACKAGE_PIN G13 [get_ports DDR3_A_D20] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D20] set_property PACKAGE_PIN H14 [get_ports DDR3_A_D14] set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D14] set_property PACKAGE_PIN J13 [get_ports DDR3_A_D11]...
  • Page 90 PACKAGE_PIN F4 [get_ports FMC1_HPC_DP7_C2M_P] set_property PACKAGE_PIN E6 [get_ports FMC1_HPC_DP7_M2C_P] set_property PACKAGE_PIN F3 [get_ports FMC1_HPC_DP7_C2M_N] set_property PACKAGE_PIN E5 [get_ports FMC1_HPC_DP7_M2C_N] set_property PACKAGE_PIN G2 [get_ports FMC1_HPC_DP6_C2M_P] set_property PACKAGE_PIN F8 [get_ports FMC1_HPC_DP6_M2C_P] set_property PACKAGE_PIN G1 [get_ports FMC1_HPC_DP6_C2M_N] www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...
  • Page 91 VC709 Board XDC Listing set_property PACKAGE_PIN E10 [get_ports FMC1_HPC_GBTCLK1_M2C_C_P] set_property PACKAGE_PIN F7 [get_ports FMC1_HPC_DP6_M2C_N] set_property PACKAGE_PIN E9 [get_ports FMC1_HPC_GBTCLK1_M2C_C_N] set_property PACKAGE_PIN G9 [get_ports FMC1_HPC_GBTCLK0_M2C_C_N] set_property PACKAGE_PIN G10 [get_ports FMC1_HPC_GBTCLK0_M2C_C_P] set_property PACKAGE_PIN H4 [get_ports FMC1_HPC_DP5_C2M_P] set_property PACKAGE_PIN G6 [get_ports FMC1_HPC_DP5_M2C_P] set_property PACKAGE_PIN H3 [get_ports FMC1_HPC_DP5_C2M_N]...
  • Page 92 Appendix C: Master XDC Listing www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 93: Appendix D: Board Setup

    Installation of the VC709 board inside a computer chassis is required when developing or testing PCI Express functionality. When the VC709 board is used inside a computer chassis (that is, plugged in to the PCIe® slot), power is provided from the ATX power supply 4-pin peripheral connector only...
  • Page 94 Caution! Do NOT plug a PC ATX power supply 6-pin connector into J18 on the VC709 board. The ATX 6-pin connector has a different pinout than J18. Connecting an ATX 6-pin connector into J18 may damage the VC709 board and void the board warranty.

  • Page 95: Appendix E: Board Specifications

    Board Specifications Dimensions Height 5.5 inch (14.0 cm) Length 10.5 inch (26.7 cm) Note: The VC709 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI Express card. Environmental Temperature Operating: 0°C to +45°C Storage: –25°C to +60°C...
  • Page 96 Appendix E: Board Specifications www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

  • Page 97: Appendix F: Additional Resources

    Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the VC709 evaluation kit and its documentation is available on these websites: Virtex-7 FPGA VC709 Connectivity Kit...
  • Page 98 UCD9248PFC, PTD08A010W, PTD08A020W, PTD08D021W, LMZ12002, TL1962ADC, TPS51200DR, PCA9548, PCA9546 Texas Instrument digital power Digital power solutions webpage Texas Instruments fusion tools Fusion Digital Power Designer graphical user interface software Texas Instruments Xilinx USB USB to GPIO Interface Adapter) Analog Devices ADP123 www.xilinx.com VC709 Evaluation Board...

  • Page 99: Appendix G: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Refer to the VC709 board master answer record concerning the CE requirements for the PC Test Environment: Virtex-7 VC709 Evaluation Kit Master Answer Record (AR 51901)

  • Page 100: Safety

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. www.xilinx.com VC709 Evaluation Board UG887 (v1.2.1) March 11, 2014...

Table of Contents