Xilinx VCU110 User Manual page 103

PCIe cable connector J136 connections are detailed in
For additional information about UltraScale PCIe functionality, see LogiCORE IP UltraScale
FPGAs Gen3 Integrated Block for PCI Express v1.0 Product Guide for Vivado Design Suite
(PG156) [Ref 8]. See
Table 1-53: VCU110 PCIe Cable Conn. J136 to FPGA U1 Connections GTH Quad 233
FPGA (U1) Pin Name
(U1) Pin
MGTHTXP0_233
MGTHTXN0_233
MGTHRXP0_233
MGTHRXN0_233
MGTHTXP1_233
MGTHTXN1_233
MGTHRXP1_233
MGTHRXN1_233
MGTHTXP2_233
MGTHTXN2_233
MGTHRXP2_233
MGTHRXN2_233
MGTHTXP3_233
MGTHTXN3_233
MGTHRXP3_233
MGTHRXN3_233
MGTREFCLK0P_233
MGTREFCLK0N_233
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
[Ref 27] for additional information about the PCI Express® standard.
FPGA
Schematic Net Name
D9 PCIE_CABLE_TX3_C_P
D8 PCIE_CABLE_TX3_C_N
D14 PCIE_CABLE_RX3_P
D13 PCIE_CABLE_RX3_N
C11 PCIE_CABLE_TX2_C_P
C10 PCIE_CABLE_TX2_C_N
C16 PCIE_CABLE_RX2_P
C15 PCIE_CABLE_RX2_N
B9 PCIE_CABLE_TX1_C_P
B8 PCIE_CABLE_TX1_C_N
B14 PCIE_CABLE_RX1_P
B13 PCIE_CABLE_RX1_N
A11 PCIE_CABLE_TX0_C_P
A10 PCIE_CABLE_TX0_C_N
A16 PCIE_CABLE_RX0_P
A15 PCIE_CABLE_RX0_N
J11 PCIE_CABLE_CLK_C_P
J10 PCIE_CABLE_CLK_C_N
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Chapter 1: VCU110 Evaluation Board Features
Table 1-53.
Connected Connected Pin
(1)
Pin Number Name
(2)
A11
(2)
A12 PETN3
B11 PERP3
B12 PERN3
(2)
A8
(2)
A9 PETN2
B8 PERP2
B9 PERN2
(2)
A5
(2)
A6 PETN1
B5 PERP1
B6 PERN1
(2)
A2
(2)
A3 PETN0
B2 PERP0
B3 PERN0
(2)
A14 CREFCLKP
(2)
A15 CREFCLKN
Connected
Device
PETP3
PETP2
PETP1
PCIe cable
connector J136
PETP0
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