Rld3 Component Memory - Xilinx VCU110 User Manual

Table 1-4: QDR2 Memory U168 18-bit SIO I/F to FPGA U1 Banks 66 and 67 (Cont'd)
FPGA (U1) Pin
AV29
AV28
AU29
AW26
AU28
AU27
AT29
AT27
AT31
AT30
AV26
NA
The VCU110 QDR2+ 18-bit SIO memory component interface adheres to the constraints
guidelines documented in the QDRII+ Design Guidelines section of the LogiCORE IP
UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide V5.0 (PG150)
[Ref 3] for Vivado Design Suite. The VCU110 QDR2 memory component interface is a 40Ω
impedance implementation.
For more details about the Cypress QDR2+ component memory, see the Cypress
CY7C2663KV18-550BZXC data sheet

RLD3 Component Memory

[Figure 1-2, callout 5]
The 1152 Mb RLD3 component memory system is comprised of two 576 Mb RLDRAM3
devices (Micron MT44K16M36RB-093E 36-bit and MT44K32M18RB-093E 18-bit) located at
U141 and U173. This memory system is connected to the XCVU190 HP banks 70, 71 and 72.
The RLD3 0.6V V
TPS51200DR linear regulator U143. The connections between RLD3 component memory
U141 and XCVU190 banks 70 and 71 are listed in
Table 1-5: RLD3 Memory U141 36-bit I/F to FPGA U1 Banks 70 and 71
FPGA (U1) Pin
C27
D29
A29
B27
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
QDR2_18B_Q9
QDR2_18B_Q10
QDR2_18B_Q11
QDR2_18B_Q12
QDR2_18B_Q13
QDR2_18B_Q14
QDR2_18B_Q15
QDR2_18B_Q16
QDR2_18B_Q17
QDR2_18B_CQ
QDR2_18B_CQ_B
NA
[Ref
termination voltage (net RLD3_VTERM_0V6) is sourced from TI
TT
Schematic Net Name
RLD3_36B_DQ0
RLD3_36B_DQ1
RLD3_36B_DQ2
RLD3_36B_DQ3
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
I/O Standard Pin Number
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
HSTL_I_DCI
NA
21].
Table 1-5.
I/O Standard
SSTL12
SSTL12
SSTL12
SSTL12
Pin Name
B2 Q9
D3 Q10
E3 Q11
F2 Q12
G3 Q13
K3 Q14
L2 Q15
N3 Q16
P3 Q17
A11 CQ
A1 CQ_B
P6 QVLD
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