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Table 1-37: VCU110 FPGA U1 GTH Quad 232 Connections
FPGA (U1) Pin
FPGA (U1)
Name
MGTHTXP0_232
MGTHTXN0_232
MGTHRXP0_232
MGTHRXN0_232
MGTHTXP1_232
MGTHTXN1_232
MGTHRXP1_232
MGTHRXN1_232
MGTHTXP2_232
MGTHTXN2_232
MGTHRXP2_232
MGTHRXN2_232
MGTHTXP3_232
MGTHTXN3_232
MGTHRXP3_232
MGTHRXN3_232
MGTREFCLK0P_232
MGTREFCLK0N_232
MGTREFCLK1P_232
MGTREFCLK1N_232
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
E7
HMC_L0TX_3_P
E6
HMC_L0TX_3_N
E2
HMC_L0RX_3_C_P
E1
HMC_L0RX_3_C_N
E11
HMC_L0TX_15_P
E10
HMC_L0TX_15_N
D4
HMC_L0RX_15_C_P
D3
HMC_L0RX_15_C_N
C7
HMC_L0TX_5_P
C6
HMC_L0TX_5_N
C2
HMC_L0RX_5_C_P
C1
HMC_L0RX_5_C_N
A7
HMC_L0TX_7_P
A6
HMC_L0TX_7_N
B4
HMC_L0RX_7_C_P
B3
HMC_L0RX_7_C_N
L11
NA
L10
NA
K13
NA
K12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin Number
A24
A23
(2)
C18
(2)
C17
E28
L0RXP_15
E27
L0RXN_15
(2)
A28
(2)
A27
L0TXN_15
D21
D20
(2)
B27
(2)
B26
B23
B22
(2)
B19
(2)
B18
NA
NA
NA
NA
Connected
Name
Device
L0RXP_3
L0RXN_3
L0TXP_3
L0TXN_3
L0TXP_15
HMC
U160
L0RXP_5
L0RXN_5
L0TXP_5
L0TXN_5
L0RXP_7
L0RXN_7
L0TXP_7
L0TXN_7
NA
NA
NA
NA
NA
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