Xilinx VCU110 User Manual page 63

Quad 232:
• REFCLK0 - not connected
• REFCLK1 - not connected
• Four GTH transceivers allocated to HMC_L0 TX and RX[12:15]_P/N (U160)
Quad 233:
• REFCLK0 - PCIE_CABLE_CLK_C_P/N (J136)
• REFCLK1 - not connected
• Four GTH transceivers allocated to PCIE_CABLE_TX and RX[0:3]_P/N (J136)
Table 1-26 through
connections, respectively.
Table 1-26: VCU110 FPGA U1 GTH Quad 220 Connections
FPGA (U1) Pin Name
MGTHTXP0_220
MGTHTXN0_220
MGTHRXP0_220
MGTHRXN0_220
MGTHTXP1_220
MGTHTXN1_220
MGTHRXP1_220
MGTHRXN1_220
MGTHTXP2_220
MGTHTXN2_220
MGTHRXP2_220
MGTHRXN2_220
MGTHTXP3_220
MGTHTXN3_220
MGTHRXP3_220
MGTHRXN3_220
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Table 1-38 list the VCU110 FPGA U1 GTH Quads 220-222 and 224-233
FPGA
Schematic Net Name
(U1) Pin
BF9 FMC_HPC0_DP0_C2M_P
BF8 FMC_HPC0_DP0_C2M_N
BF14 FMC_HPC0_DP0_M2C_P
BF13 FMC_HPC0_DP0_M2C_N
BE11 FMC_HPC0_DP1_C2M_P
BE10 FMC_HPC0_DP1_C2M_N
BD14 FMC_HPC0_DP1_M2C_P
BD13 FMC_HPC0_DP1_M2C_N
BE7 FMC_HPC0_DP2_C2M_P
BE6 FMC_HPC0_DP2_C2M_N
BF4 FMC_HPC0_DP2_M2C_P
BF3 FMC_HPC0_DP2_M2C_N
BD9 FMC_HPC0_DP3_C2M_P
BD8 FMC_HPC0_DP3_C2M_N
BD4 FMC_HPC0_DP3_M2C_P
BD3 FMC_HPC0_DP3_M2C_N
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Chapter 1: VCU110 Evaluation Board Features
Connected Connected Pin
(1)
Pin Number Name
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
A22 DP1_C2M_P
A23 DP1_C2M_N
A2 DP1_M2C_P
A3 DP1_M2C_N
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
A7 DP2_M2C_N
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
A11 DP3_M2C_N
Send Feedback
Connected
Device
FMC HPC0
J22
63