Gpio Dip Switch - Xilinx KCU116 User Manual

GPIO DIP Switch

[Figure 2-1, callout 25]
Figure 3-24 shows the GPIO DIP switch circuit.
X-Ref Target - Figure 3-24
Table 3-20 lists the GPIO connections to FPGA U1.
Table 3‐20: KCU116 GPIO Connections to FPGA U1
FPGA Pin (U1)
GPIO LEDs (active-High)
BANK 86
BANK 86
BANK 86
BANK 86
BANK 86
BANK 86
BANK 86
BANK 86
Directional Pushbuttons (active-High)
BANK 86
BANK 86
BANK 86
BANK 86
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Figure 3‐24: GPIO DIP Switch
Schematic Net
Name
C9 GPIO_LED_0
D9 GPIO_LED_1
E10 GPIO_LED_2
E11 GPIO_LED_3
F9 GPIO_LED_4
F10 GPIO_LED_5
G9 GPIO_LED_6
G10 GPIO_LED_7
A10 GPIO_SW_N
B11 GPIO_SW_E
B10 GPIO_SW_W
C11 GPIO_SW_S
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Chapter 3: Board Component Descriptions
X18537-042017
I/O Standard
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
Send Feedback
GPIO
DS38.1
DS37.1
DS39.1
DS40.1
DS41.1
DS42.1
DS43.1
DS44.1
SW18.3
SW22.3
SW14.3
SW16.3
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