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Table 1-25: VCU110 FPGA U1 GTY Quad 133 Connections
FPGA (U1) Pin Name
MGTYTXP0_133
MGTYTXN0_133
MGTYRXP0_133
MGTYRXN0_133
MGTYTXP1_133
MGTYTXN1_133
MGTYRXP1_133
MGTYRXN1_133
MGTYTXP2_133
MGTYTXN2_133
MGTYRXP2_133
MGTYRXN2_133
MGTYTXP3_133
MGTYTXN3_133
MGTYRXP3_133
MGTYRXN3_133
MGTREFCLK0P_133
MGTREFCLK0N_133
MGTREFCLK1P_133
MGTREFCLK1N_133
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
For additional information on GTH transceivers, see UltraScale FPGAs GTY Transceivers User
Guide (UG578)
Also see UltraScale FPGAs Transceivers Wizard Product Guide for Vivado Design Suite
(PG182)
[Ref
6].
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
(U1) Pin
D38
ILKN_TX16_P
D39
ILKN_TX16_N
D33
ILKN_RX16_C_P
D34
ILKN_RX16_C_N
C36
ILKN_TX17_P
C37
ILKN_TX17_N
C31
ILKN_RX17_C_P
C32
ILKN_RX17_C_N
B38
ILKN_TX18_P
B39
ILKN_TX18_N
B33
ILKN_RX18_C_P
B34
ILKN_RX18_C_N
A36
ILKN_TX19_P
A37
ILKN_TX19_N
A31
ILKN_RX19_C_P
A32
ILKN_RX19_C_N
J36
ILKN_SI5328_OUT2_BUF5_C_P
J37
ILKN_SI5328_OUT2_BUF5_C_N
H34
H35
[Ref
5].
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
A11
A12
(2)
J14
(2)
J15
C11
C12
(2)
D11
(2)
D12
A14
A15
(2)
B14
(2)
B15
C14
C15
(2)
D14
(2)
D15
(2)
35
(2)
34
NA
NA
NA
NA
Connected
Connected
Pin Name
Device
TX16_P
TX16_N
RX16_P
RX16_N
TX17_P
TX17_N
RX17_P
RX17_N
Interlaken
J121
TX18_P
TX18_N
RX18_P
RX18_N
TX19_P
TX19_N
RX19_P
RX19_N
CKOUT2_P
SI5328
U181
CKOUT2_N
NA
NA
NA
60
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