Xilinx VCU110 User Manual page 117

Table 1-62: J2 VITA 57.1 FMC HPC1 Sections C and D to FPGA U1 Connections
J2
FMC Schematic
HPC1 Net Name
Pin
C2 FMC_HPC1_DP0_C2M_P
C3 FMC_HPC1_DP0_C2M_N
C6 FMC_HPC1_DP0_M2C_P
C7 FMC_HPC1_DP0_M2C_N
C10 FMC_HPC1_LA06_P
C11 FMC_HPC1_LA06_N
C14 FMC_HPC1_LA10_P
C15 FMC_HPC1_LA10_N
C18 NA
C19 NA
C22 NA
C23 NA
C26 NA
C27 NA
C30 FMC_HPC1_IIC_SCL
C31 FMC_HPC1_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
Notes:
1. No I/O Standards are associated with MGT connections.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J2
U1
I/O FMC
FPGA
Standard HPC1
Pin
Pin
(1)
AR7 D1
(1)
AR6 D4
(1)
AR2 D5
(1)
AR1 D8
LVCMOS18 AR36 D9
LVCMOS18 AT36 D11
LVCMOS18 AR32 D12
LVCMOS18 AT32 D14
NA D15
NA D17
NA D18
NA D20
NA D21
NA D23
U80.13 D24
U80.12 D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Chapter 1: VCU110 Evaluation Board Features
Schematic
Net Name
VADJ_1V8_PGOOD
FMC_HPC1_GBTCLK0_M2C_P
FMC_HPC1_GBTCLK0_M2C_N
FMC_HPC1_LA01_CC_P
FMC_HPC1_LA01_CC_N
FMC_HPC1_LA05_P
FMC_HPC1_LA05_N
FMC_HPC1_LA09_P
FMC_HPC1_LA09_N
NA
NA
NA
NA
NA
NA
NA
NA
FMC_HPC1_TCK_BUF
FPGA_TDO_FMC_TDI_BUF
FMC_HPC0_TDO_HPC1_TDI
UTIL_3V3
FMC_HPC1_TMS_BUF
NA
NA
UTIL_3V3
UTIL_3V3
UTIL_3V3
U1
I/O
FPGA
Standard
Pin
LVCMOS18 AP18
(1)
AG11
(1)
AG10
LVCMOS18 AR35
LVCMOS18 AT35
LVCMOS18 BC29
LVCMOS18 AU32
LVCMOS18 AV31
LVCMOS18 AW31
NA
NA
NA
NA
NA
NA
NA
NA
U19.16
U19.21
U26.2
U19.19
NA
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