Xilinx VCU110 User Manual page 112

Table 1-57: J22 VITA 57.1 FMC HPC0 Sections C and D to FPGA U1 Connections
J22
FMC Schematic
HPC0 Net Name
Pin
C2 FMC_HPC0_DP0_C2M_P
C3 FMC_HPC0_DP0_C2M_N
C6 FMC_HPC0_DP0_M2C_P
C7 FMC_HPC0_DP0_M2C_N
C10 FMC_HPC0_LA06_P
C11 FMC_HPC0_LA06_N
C14 FMC_HPC0_LA10_P
C15 FMC_HPC0_LA10_N
C18 NA
C19 NA
C22 NA
C23 NA
C26 NA
C27 NA
C30 FMC_HPC0_IIC_SCL
C31 FMC_HPC0_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
Notes:
1. No I/O Standards are associated with MGT connections.
2. Series capacitor coupled.
3. VADJ_1V8_PGOOD level-shifted from 3.3V to 1.8V at TXS0108E U44.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J22
U1
I/O FMC
FPGA
Standard HPC0
Pin
Pin
(1)
BF9 D1
(1)
BF8 D4
(1)
BF14 D5
(1)
BF13 D8
LVDS BD30 D9
LVDS BE30 D11
LVDS AR32 D12
LVDS AT32 D14
NA D15
NA D17
NA D18
NA D20
NA D21
NA D23
U80.9 D24
U80.8 D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Chapter 1: VCU110 Evaluation Board Features
Schematic
Net Name
(3)
VADJ_1V8_PGOOD
FMC_HPC0_GBTCLK0_M2C_P
FMC_HPC0_GBTCLK0_M2C_N
FMC_HPC0_LA01_CC_P
FMC_HPC0_LA01_CC_N
FMC_HPC0_LA05_P
FMC_HPC0_LA05_N
FMC_HPC0_LA09_P
FMC_HPC0_LA09_N
NA
NA
NA
NA
NA
NA
NA
NA
FMC_HPC0_TCK_BUF
FPGA_TDO_FMC_TDI_BUF
FMC_HPC0_TDO_HPC1_TDI
VCC3V3
FMC_HPC0_TMS_BUF
NA
GA1 = 0 = GND
UTIL_3V3
UTIL_3V3
UTIL_3V3
U1
I/O
FPGA
Standard
Pin
LVCMOS18 AP18
(2) (1)
AL11
(2) (1)
AL10
LVDS AY32
LVDS BA32
LVDS BC29
BC30
LVDS
BC31
LVDS
LVDS BD31
NA
NA
NA
NA
NA
NA
NA
NA
U19.17
U19.21
U132.1
U19.20
112
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