Table of Contents
Advertisement
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AM26
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AN25
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AN26
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AP25
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AP23
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AU26
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AT26
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR25
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AT24
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR24
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AU22
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AT22
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR22
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR23
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AN28
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AM29
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AN29
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AM31
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AP28
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AN31
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR27
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR29
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AR30
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AV29
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AV28
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AU29
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AW26
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AU28
IOSTANDARD
HSTL_I_DCI
PACKAGE_PIN AU27
IOSTANDARD
HSTL_I_DCI
www.xilinx.com
Appendix D:
Master Constraints File Listing
[get_ports "QDR2_18B_D3"]
[get_ports "QDR2_18B_D4"]
[get_ports "QDR2_18B_D4"]
[get_ports "QDR2_18B_D5"]
[get_ports "QDR2_18B_D5"]
[get_ports "QDR2_18B_D6"]
[get_ports "QDR2_18B_D6"]
[get_ports "QDR2_18B_D7"]
[get_ports "QDR2_18B_D7"]
[get_ports "QDR2_18B_D8"]
[get_ports "QDR2_18B_D8"]
[get_ports "QDR2_18B_D9"]
[get_ports "QDR2_18B_D9"]
[get_ports "QDR2_18B_D10"]
[get_ports "QDR2_18B_D10"]
[get_ports "QDR2_18B_D11"]
[get_ports "QDR2_18B_D11"]
[get_ports "QDR2_18B_D12"]
[get_ports "QDR2_18B_D12"]
[get_ports "QDR2_18B_D13"]
[get_ports "QDR2_18B_D13"]
[get_ports "QDR2_18B_D14"]
[get_ports "QDR2_18B_D14"]
[get_ports "QDR2_18B_D15"]
[get_ports "QDR2_18B_D15"]
[get_ports "QDR2_18B_D16"]
[get_ports "QDR2_18B_D16"]
[get_ports "QDR2_18B_D17"]
[get_ports "QDR2_18B_D17"]
[get_ports "QDR2_18B_Q0"]
[get_ports "QDR2_18B_Q0"]
[get_ports "QDR2_18B_Q1"]
[get_ports "QDR2_18B_Q1"]
[get_ports "QDR2_18B_Q2"]
[get_ports "QDR2_18B_Q2"]
[get_ports "QDR2_18B_Q3"]
[get_ports "QDR2_18B_Q3"]
[get_ports "QDR2_18B_Q4"]
[get_ports "QDR2_18B_Q4"]
[get_ports "QDR2_18B_Q5"]
[get_ports "QDR2_18B_Q5"]
[get_ports "QDR2_18B_Q6"]
[get_ports "QDR2_18B_Q6"]
[get_ports "QDR2_18B_Q7"]
[get_ports "QDR2_18B_Q7"]
[get_ports "QDR2_18B_Q8"]
[get_ports "QDR2_18B_Q8"]
[get_ports "QDR2_18B_Q9"]
[get_ports "QDR2_18B_Q9"]
[get_ports "QDR2_18B_Q10"]
[get_ports "QDR2_18B_Q10"]
[get_ports "QDR2_18B_Q11"]
[get_ports "QDR2_18B_Q11"]
[get_ports "QDR2_18B_Q12"]
[get_ports "QDR2_18B_Q12"]
[get_ports "QDR2_18B_Q13"]
[get_ports "QDR2_18B_Q13"]
[get_ports "QDR2_18B_Q14"]
[get_ports "QDR2_18B_Q14"]
137
Send Feedback
Advertisement
Table of Contents
