Xilinx VCU110 User Manual page 114

Table 1-59: J22 VITA 57.1 FMC HPC0 Sections G and H to FPGA U1 Connections
J22
FMC Schematic
HPC0 Net Name
Pin
G2 NA
G3 NA
G6 FMC_HPC0_LA00_CC_P
G7 FMC_HPC0_LA00_CC_N
G9 FMC_HPC0_LA03_P
G10 FMC_HPC0_LA03_N
G12 FMC_HPC0_LA08_P
G13 FMC_HPC0_LA08_N
G15 NA
G16 NA
G18 NA
G19 NA
G21 NA
G22 NA
G24 NA
G25 NA
G27 NA
G28 NA
G30 NA
G31 NA
G33 NA
G34 NA
G36 NA
G37 NA
G39 VADJ _1V8_FPGA
Notes:
1. FMC_HPC0_PRSNT_M2C_B level-shifted from 3.3V to 1.8V at U44.
2. FMC_HPC0_PRSNT_M2C_B level-shifted from 3.3V to 1.8V at TXS0108E U109, connected to U111 pin R13.
3. FMC_HPC0_VREF_A_M2C is the source of U1 bank 68 Vref pin AM32 connected via DNP series resistor R1674, and U1 bank
84 Vref pin AM17 via DNP resistor R796.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
J22
U1
I/O FMC
FPGA
Standard HPC0
Pin
Pin
NA H1
NA H2
LVDS AY34 H4
LVDS AY35 H5
LVDS BA34 H7
LVDS BB34 H8
LVDS BE29 H10
LVDS BF29 H11
NA H13
NA H14
NA H16
NA H17
NA H19
NA H20
NA H22
NA H23
NA H25
NA H26
NA H28
NA H29
NA H31
NA H32
NA H34
NA H35
H37
H38
H40
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Chapter 1: VCU110 Evaluation Board Features
Schematic
Net Name
(3)
FMC_HPC0_VREF_A_M2C
(1)(2)
FMC_HPC0_PRSNT_M2C_B
FMC_HPC0_CLK0_M2C_P
FMC_HPC0_CLK0_M2C_N
FMC_HPC0_LA02_P
FMC_HPC0_LA02_N
FMC_HPC0_LA04_P
FMC_HPC0_LA04_N
FMC_HPC0_LA07_P
FMC_HPC0_LA07_N
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VADJ _1V8_FPGA
I/O U1 FPGA
Standard Pin
NA
R13
LVCMOS18
LVDS AW33
AY33
LVDS
BA36
LVDS
BB36
LVDS
LVDS BB32
BB33
LVDS
BA31
LVDS
LVDS BB31
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
114
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