Xilinx VCU110 User Manual page 138

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# RLD3 18-bit
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VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN AT29
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AT27
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AT31
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AT30
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AV26
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AN24
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AT25
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AW25
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN AU23
IOSTANDARD DIFF_HSTL_I_[get_ports "QDR2_18B_K_P"]
PACKAGE_PIN AU24
IOSTANDARD DIFF_HSTL_I_[get_ports "QDR2_18B_K_N"]
PACKAGE_PIN BF24
IOSTANDARD HSTI_I
PACKAGE_PIN AY23
IOSTANDARD HSTL_I_DCI
PACKAGE_PIN A20
IOSTANDARD SSTL12
PACKAGE_PIN F20
IOSTANDARD SSTL12
PACKAGE_PIN E18
IOSTANDARD SSTL12
PACKAGE_PIN H18
IOSTANDARD SSTL12
PACKAGE_PIN G18
IOSTANDARD SSTL12
PACKAGE_PIN H19
IOSTANDARD SSTL12
PACKAGE_PIN J19
IOSTANDARD SSTL12
PACKAGE_PIN F18
IOSTANDARD SSTL12
PACKAGE_PIN A19
IOSTANDARD SSTL12
PACKAGE_PIN H20
IOSTANDARD SSTL12
PACKAGE_PIN J20
IOSTANDARD SSTL12
PACKAGE_PIN E19
IOSTANDARD SSTL12
PACKAGE_PIN A18
IOSTANDARD SSTL12
PACKAGE_PIN B20
IOSTANDARD SSTL12
PACKAGE_PIN G20
IOSTANDARD SSTL12
PACKAGE_PIN K16
IOSTANDARD SSTL12
PACKAGE_PIN L15
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Appendix D: Master Constraints File Listing
[get_ports "QDR2_18B_Q15"]
[get_ports "QDR2_18B_Q15"]
[get_ports "QDR2_18B_Q16"]
[get_ports "QDR2_18B_Q16"]
[get_ports "QDR2_18B_Q17"]
[get_ports "QDR2_18B_Q17"]
[get_ports "QDR2_18B_CQ"]
[get_ports "QDR2_18B_CQ"]
[get_ports "QDR2_18B_CQ_B"]
[get_ports "QDR2_18B_CQ_B"]
[get_ports "QDR2_18B_BWS0_B"]
[get_ports "QDR2_18B_BWS0_B"]
[get_ports "QDR2_18B_BWS1_B"]
[get_ports "QDR2_18B_BWS1_B"]
[get_ports "QDR2_18B_DOFF_B"]
[get_ports "QDR2_18B_DOFF_B"]
[get_ports "QDR2_18B_K_P"]
[get_ports "QDR2_18B_K_N"]
[get_ports "QDR2_18B_RPS_B"]
[get_ports "QDR2_18B_RPS_B"]
[get_ports "QDR2_18B_WPS_B"]
[get_ports "QDR2_18B_WPS_B"]
[get_ports "RLD3_18B_A0"]
[get_ports "RLD3_18B_A0"]
[get_ports "RLD3_18B_A3"]
[get_ports "RLD3_18B_A3"]
[get_ports "RLD3_18B_A4"]
[get_ports "RLD3_18B_A4"]
[get_ports "RLD3_18B_A5"]
[get_ports "RLD3_18B_A5"]
[get_ports "RLD3_18B_A8"]
[get_ports "RLD3_18B_A8"]
[get_ports "RLD3_18B_A9"]
[get_ports "RLD3_18B_A9"]
[get_ports "RLD3_18B_A10"]
[get_ports "RLD3_18B_A10"]
[get_ports "RLD3_18B_A13"]
[get_ports "RLD3_18B_A13"]
[get_ports "RLD3_18B_A14"]
[get_ports "RLD3_18B_A14"]
[get_ports "RLD3_18B_A17"]
[get_ports "RLD3_18B_A17"]
[get_ports "RLD3_18B_A18"]
[get_ports "RLD3_18B_A18"]
[get_ports "RLD3_18B_BA0"]
[get_ports "RLD3_18B_BA0"]
[get_ports "RLD3_18B_BA1"]
[get_ports "RLD3_18B_BA1"]
[get_ports "RLD3_18B_BA2"]
[get_ports "RLD3_18B_BA2"]
[get_ports "RLD3_18B_BA3"]
[get_ports "RLD3_18B_BA3"]
[get_ports "RLD3_18B_DQ0"]
[get_ports "RLD3_18B_DQ0"]
[get_ports "RLD3_18B_DQ1"]
138
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