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Table 1-34: VCU110 FPGA U1 GTH Quad 229 Connections
FPGA (U1) Pin Name FPGA (U1) Pin
MGTHTXP0_229
MGTHTXN0_229
MGTHRXP0_229
MGTHRXN0_229
MGTHTXP1_229
MGTHTXN1_229
MGTHRXP1_229
MGTHRXN1_229
MGTHTXP2_229
MGTHTXN2_229
MGTHRXP2_229
MGTHRXN2_229
MGTHTXP3_229
MGTHTXN3_229
MGTHRXP3_229
MGTHRXN3_229
MGTREFCLK0P_229
MGTREFCLK0N_229
MGTREFCLK1P_229
MGTREFCLK1N_229
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net
(1)
Name
R7
HMC_L0TX_12_P
R6
HMC_L0TX_12_N
R2
HMC_L0RX_12_C_P
R1
HMC_L0RX_12_C_N
P9
HMC_L0TX_9_P
P8
HMC_L0TX_9_N
P4
HMC_L0RX_9_C_P
P3
HMC_L0RX_9_C_N
N7
HMC_L0TX_13_P
N6
HMC_L0TX_13_N
N2
HMC_L0RX_13_C_P
N1
HMC_L0RX_13_C_N
M9
HMC_L0TX_8_P
M8
HMC_L0TX_8_N
M4
HMC_L0RX_8_C_P
M3
HMC_L0RX_8_C_N
U11
NA
U10
NA
T13
NA
T12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
Pin Number
H25
L0RXP_12
H24
L0RXN_12
(2)
J28
L0TXP_12
(2)
J27
L0TXN_12
M28
M27
L0RXN_9
(2)
L26
(2)
L25
L0TXN_9
G26
L0RXP_13
G25
L0RXN_13
(2)
H29
L0TXP_13
(2)
H28
L0TXN_13
L30
L29
L0RXN_8
(2)
K27
(2)
K26
L0TXN_8
NA
NA
NA
NA
Connected
Name
Device
L0RXP_9
L0TXP_9
HMC
U160
L0RXP_8
L0TXP_8
NA
NA
NA
NA
NA
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