Jtag Chain Fmc Connector Bypass; Clock Generation - Xilinx VCU110 User Manual

JTAG Chain FMC Connector Bypass

When an FMC mezzanine card is attached to the VCU110 board it is automatically added to
the JTAG chain through electronically controlled single-pole single-throw (SPST) switches
U26 (HPC0) and U132 (HPC1). The SPST switches are in a normally closed state and
transition to an open state when an FMC mezzanine card is attached.
• Switch U26 adds an attached FMC HPC0 J22 mezzanine card to the FPGAs JTAG chain as
determined by the FMC_HPC0_PRSNT_M2C_B signal.
• Switch U132 adds an attached FMC HPC1 J2 mezzanine card to the FPGAs JTAG chain as
determined by the FMC_HPC1_PRSNT_M2C_B signal.
The attached FMC card must implement a TDI-to-TDO connection through a device or
bypass jumper to ensure that the JTAG chain connects to the FPGA U1.
The JTAG connectivity on the VCU110 board allows a host computer to download bitstreams
to the FPGA using Xilinx configuration software. In addition, the JTAG connector allows
debug tools such as the Vivado serial I/O analyzer or a software debugger to access the
FPGA. The Xilinx configuration software tool can also program the dual Quad SPI Flash
memory.

Clock Generation

The VCU110 evaluation board provides fourteen clock sources to the FPGA and eleven to
other board components (25 total), as listed in
Table 1-11: VCU110 Board Clock Sources
Clock Name
System clock 300 MHz
System clock 125 MHz
EMC clock 90 MHz
System controller U111
clock 33.333 MHz
User clock
10 MHz - 810 MHz
Jitter-attenuating clock
multiplier
Jitter-attenuating clock
multiplier
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Clock Reference
Designator
Silicon Labs Si5335A LVDS any frequency Quad clock generator
U122
CLK0. (SYSCLK_300_P/N)
Silicon Labs Si5335A LVDS any frequency Quad clock generator
U122
CLK1. (CLK_125MHZ_P/N)
Silicon Labs Si5335A 1.8V LVCMOS single-ended any frequency
U122
Quad clock generator CLK2A. (FPGA_EMCCLK)
Silicon Labs Si5335A 1.8V LVCMOS single-ended any frequency
U122
Quad clock generator CLK3A. (SYSCTLR_CLK)
Silicon Labs Si570 LVDS I2C programmable oscillator, 156.250 MHz
U32
default. U32 (USER_SI570_CLOCK_P/N)
Silicon Labs Si5328C LVDS precision clock multiplier CKOUT1
U57
(HMC_SI5328_OUT1_P /N)
Silicon Labs Si5328C LVDS precision clock
U57/U165 multiplier/jitter-attenuator CKOUT2 drives U165 Quad clock buffer
(two buffered clocks HMC_SI5328_OUT2_BUF[1:2]_C_P /N)
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Chapter 1: VCU110 Evaluation Board Features
Table 1-11.
Description
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