Xilinx VCU110 User Manual page 40

The 300 MHz system clock circuit is shown in
X-Ref Target - Figure 1-8
C853 C852 C851 C850
1 1 1
0.1UF 0.1UF 0.1UF 0.1UF
25V 2 25V 2 25V 2 25V
25MHZ
X1
2
GND1
4
GND2
X2
50PPM
X6
GND
SYSCLK_RESET
SYSCLK_OEB_ALL
R793 R792
1 1
4.70K 4.70K
1/16W 1/16W
2 2
1% 1%
Three additional clocks are sourced from the U122 Quad clock generator:
• 125 MHz LVDS signal pair CLK_125MHZ_P and CLK_125MHZ_N, connected to XCVU190
FPGA U1 Bank 65 pins AV20 and AW20, respectively.
• 90.0 MHz single-ended 1.8V LVCMOS, series resistor coupled FPGA_EMCCLK,
connected to XCVU190 FPGA U1 Bank 65 dedicated EMCCLK input pin BE20.
• 33.3333 MHz single-ended 1.8V LVCMOS, series resistor coupled SYSCTLR_CLK,
connected to system controller XC7Z010 Zynq AP SoC U111 Bank 500 dedicated
PS_CLK input pin C7.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
SYS_1V8
C849 C848
1 1 1
0.1UF 0.1UF
2 25V 2 25V 2
1
GND
3
1
VCC1V8 XA
2 XB
3
RESET
5
OEB_ALL
R802 R803
1 1
DNP 0
DNP 1/10W
2 2
DNP 5%
NC 8
LOS
12
FS0
19
FS1
R804 R801
1 1
0 DNP U122
1/10W DNP
2 2
5% DNP
GND
GND
Figure 1-8: 300 MHz System Clock
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
Figure 1-8.
SYSCLK_300_C_P
SYSCLK_300_C_N
SI5335A-B02436-GM
22
CLK0A
21
CLK0B
CLK_125MHZ_P
18
CLK1A
CLK_125MHZ_N
17
CLK1B
FPGA_EMCCLK_R FPGA_EMCCLK
14
CLK2A
13 NC
CLK2B
SYSCTLR_CLK
SYSCTLR_CLK_R
10
CLK3A
9 NC
CLK3B
QFN24_4X4MM
VCC1V2_FPGA
R1150 R1151
1 1
1.00K 1.00K
1/16W 1/16W
2 2
1% 1%
SYSCLK_300_P
SYSCLK_300_N
R1152 R1153
1 1
1.00K 1.00K
1/16W 1/16W
2 2
1% 1%
GND
125 MHz LVDS
90.0 MHz LVCMOS
33.333 MHz LVCMOS
40
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