Hybrid Memory Cube - Xilinx VCU110 User Manual

The connections between the dual Quad SPI components U182, U183 and XCVU190 banks
0 and 65 are listed in
Table 1-7: Dual-QSPI Memory U182, U183 I/F to FPGA U1 Banks 0 and 65
FPGA (U1) Schematic Net
Pin
AM14
AK14
AF16
AH14
AF14
AB16
BE19
BF19
BD18
BE18
AP20
AB16
Notes:
1. Bank 0 V = 1.8V; Bank 0 I/O standards are not specified.
CCO

Hybrid Memory Cube

[Figure 1-2, callout 7]
The HMC component memory system is comprised of one 16-lane 4 GB device (Micron
MT43A4G80100) located at U160. This memory system is connected to the XCVU190 MGTH
banks 225-232 (8 MGTH Quads).
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Table 1-7.
I/O Standard
Name
(1)
QSPI0_IO0
(1)
QSPI0_IO1
(1)
QSPI0_IO2
(1)
QSPI0_IO3
(1)
QSPI0_CS_B
(1)
FPGA_CCLK
QSPI1_IO0 LVCMOS18
QSPI1_IO1 LVCMOS18
QSPI1_IO2 LVCMOS18
QSPI1_IO3 LVCMOS18
QSPI1_CS_B LVCMOS18
(1)
FPGA_CCLK
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Chapter 1: VCU110 Evaluation Board Features
QSPI Memory
Pin Number Pin Name
D3 DQ0
D2 DQ1
C4 DQ2_W_B
D4 DQ3_HOLD_B
C2 S_B
B2 C
D3 DQ0
D2 DQ1
C4 DQ2_W_B
D4 DQ3_HOLD_B
C2 S_B
B2 C
Reference
Designator
U182
U182
U182
U182
U182
U182
U183
U183
U183
U183
U183
U183
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