Xilinx VCU110 User Manual page 148

# RESET PUSH-BUTTON SWITCH
set_property
set_property
# LEDS
set_property
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set_property
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set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
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set_property
# PMOD 2x6 RT. ANGLE RECEPTACLE
set_property
set_property
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# FAN CONTROL
set_property
set_property
set_property
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# PMBUS
set_property
set_property
set_property
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# PCIE CABLE CONNECTOR
set_property
set_property
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN J29
IOSTANDARD LVCMOS12
PACKAGE_PIN N25
IOSTANDARD LVCMOS12
PACKAGE_PIN N22
IOSTANDARD LVCMOS12
PACKAGE_PIN M22
IOSTANDARD LVCMOS12
PACKAGE_PIN M26
IOSTANDARD LVCMOS12
PACKAGE_PIN M25
IOSTANDARD LVCMOS12
PACKAGE_PIN P24
IOSTANDARD LVCMOS12
PACKAGE_PIN N24
IOSTANDARD LVCMOS12
PACKAGE_PIN N23
IOSTANDARD LVCMOS12
PACKAGE_PIN L23
IOSTANDARD LVCMOS12
PACKAGE_PIN J22
IOSTANDARD LVCMOS12
PACKAGE_PIN J21
IOSTANDARD LVCMOS12
PACKAGE_PIN J25
IOSTANDARD LVCMOS12
PACKAGE_PIN K23
IOSTANDARD LVCMOS12
PACKAGE_PIN K21
IOSTANDARD LVCMOS12
PACKAGE_PIN L24
IOSTANDARD LVCMOS12
PACKAGE_PIN H25
IOSTANDARD LVCMOS12
PACKAGE_PIN AT21
IOSTANDARD LVCMOS18
PACKAGE_PIN AT19
IOSTANDARD LVCMOS18
PACKAGE_PIN AU21
IOSTANDARD LVCMOS18
PACKAGE_PIN K24
IOSTANDARD LVCMOS12
PACKAGE_PIN AN16
IOSTANDARD LVCMOS18
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Appendix D: Master Constraints File Listing
[get_ports "CPU_RESET"]
[get_ports "CPU_RESET"]
[get_ports "GPIO_LED_0_LS"]
[get_ports "GPIO_LED_0_LS"]
[get_ports "GPIO_LED_1_LS"]
[get_ports "GPIO_LED_1_LS"]
[get_ports "GPIO_LED_2_LS"]
[get_ports "GPIO_LED_2_LS"]
[get_ports "GPIO_LED_3_LS"]
[get_ports "GPIO_LED_3_LS"]
[get_ports "GPIO_LED_4_LS"]
[get_ports "GPIO_LED_4_LS"]
[get_ports "GPIO_LED_5_LS"]
[get_ports "GPIO_LED_5_LS"]
[get_ports "GPIO_LED_6_LS"]
[get_ports "GPIO_LED_6_LS"]
[get_ports "GPIO_LED_7_LS"]
[get_ports "GPIO_LED_7_LS"]
[get_ports "PMOD0_0_LS"]
[get_ports "PMOD0_0_LS"]
[get_ports "PMOD0_1_LS"]
[get_ports "PMOD0_1_LS"]
[get_ports "PMOD0_2_LS"]
[get_ports "PMOD0_2_LS"]
[get_ports "PMOD0_3_LS"]
[get_ports "PMOD0_3_LS"]
[get_ports "PMOD0_4_LS"]
[get_ports "PMOD0_4_LS"]
[get_ports "PMOD0_5_LS"]
[get_ports "PMOD0_5_LS"]
[get_ports "PMOD0_6_LS"]
[get_ports "PMOD0_6_LS"]
[get_ports "PMOD0_7_LS"]
[get_ports "PMOD0_7_LS"]
[get_ports "SM_FAN_PWM"]
[get_ports "SM_FAN_PWM"]
[get_ports "SM_FAN_TACH"]
[get_ports "SM_FAN_TACH"]
[get_ports "PMBUS_ALERT_FPGA"]
[get_ports "PMBUS_ALERT_FPGA"]
[get_ports "MAXIM_CABLE_B_FPGA"]
[get_ports "MAXIM_CABLE_B_FPGA"]
[get_ports "PCIE_CABLE_FPGA_CPERST_B"]
[get_ports "PCIE_CABLE_FPGA_CPERST_B"]
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