Fpga Mezzanine Card (Fmc) Interface - Xilinx VCU110 User Manual

Table 1-55: VCU110 ExaMAX J116 to FPGA U1 GTY Quads 121-120 Connections (Cont'd)
ExaMAX
ExaMAX J116
J116 Pin
Pin Number
Name
TX5_P
TX5_N
RX5_P
RX5_N
TX6_P
TX6_N
RX6_P
RX6_N
TX7_P
TX7_N
RX7_P
RX7_N
TX8_P
TX8_N
RX8_P
RX8_N
Notes:
1. MGT connections I/O standard not applicable.

FPGA Mezzanine Card (FMC) Interface

[Figure 1-2, callouts 33, 34]
The VCU110 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC)
specification by providing subset implementations of high pin count connectors at J22
(HPC0) and J2 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400 pins.
The connectors are keyed so that a mezzanine card, when installed in either of these FMC
connectors on the VCU110 evaluation board, faces away from the board.
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a –3 dB insertion loss point within a two-level signaling environment.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net
(1)
Name
K6 EXAMAX_TX5_P
L6 EXAMAX_TX5_N
B6 EXAMAX_RX5_P
C6 EXAMAX_RX5_N
H6 EXAMAX_TX6_P
I6 EXAMAX_TX6_N
E6 EXAMAX_RX6_P
F6 EXAMAX_RX6_N
L7 EXAMAX_TX7_P
M7 EXAMAX_TX7_N
C7 EXAMAX_RX7_P
D7 EXAMAX_RX7_N
I7 EXAMAX_TX8_P
J7 EXAMAX_TX8_N
F7 EXAMAX_RX8_P
G7 EXAMAX_RX8_N
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
FPGA (U1) FPGA (U1) Pin
Pin Name
AT38 MGTYTXP3_120
AT39 MGTYTXN3_120
AT43 MGTYRXP3_120
AT44 MGTYRXN3_120
AU40 MGTYTXP2_120
AU41 MGTYTXN2_120
AU45 MGTYRXP2_120
AU46 MGTYRXN2_120
AV38 MGTYTXP1_120
AV39 MGTYTXN1_120
AV43 MGTYRXP1_120
AV44 MGTYRXN1_120
AW40 MGTYTXP0_120
AW41 MGTYTXN0_120
AW45 MGTYRXP0_120
AW46 MGTYRXN0_120
MGT Quad
GTY Quad 120
109
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