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Table 1-3: I/O Bank Voltage Rails (Cont'd)
FPGA (U1) Bank
HR Bank 84
HR Bank 94
QDR2+ Component Memory
[Figure
1-2, callout 4]
The 144 Mb QDR2+ component memory system is comprised of one 18-bit separate I/O
(SIO) device (Cypress CY7C2663KV18-550BZXC) located at U168. This memory system is
connected to the XCVU190 HP banks 66 and 67. The DDR4 0.75V V
(net QDR2_VTERM_0V75) is sourced from TI TPS51200DR linear regulator U167. The
connections between QDR2 component memory U168 and XCVU190 banks 66 and 67 are
listed in
Table
Table 1-4: QDR2 Memory U168 18-bit SIO I/F to FPGA U1 Banks 66 and 67
FPGA (U1) Pin
AM23
AM24
AN23
AP22
AM26
AN25
AN26
AP25
AP23
AU26
AT26
AR25
AT24
AR24
AU22
AT22
AR22
AR23
BA22
AY24
AW23
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Power Supply Rail Net Name
VCC1V8_FPGA
VCC1V8_FPGA
1-4.
Schematic Net Name
QDR2_18B_D0
QDR2_18B_D1
QDR2_18B_D2
QDR2_18B_D3
QDR2_18B_D4
QDR2_18B_D5
QDR2_18B_D6
QDR2_18B_D7
QDR2_18B_D8
QDR2_18B_D9
QDR2_18B_D10
QDR2_18B_D11
QDR2_18B_D12
QDR2_18B_D13
QDR2_18B_D14
QDR2_18B_D15
QDR2_18B_D16
QDR2_18B_D17
QDR2_18B_A0
QDR2_18B_A1
QDR2_18B_A2
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
Voltage
1.8V
1.8V
I/O Standard
Pin Number
HSTL_I_DCI
P10
HSTL_I_DCI
N11
HSTL_I_DCI
M11
HSTL_I_DCI
K10
HSTL_I_DCI
J11
HSTL_I_DCI
G11
HSTL_I_DCI
E10
HSTL_I_DCI
D11
HSTL_I_DCI
C11
HSTL_I_DCI
B3
HSTL_I_DCI
C3
HSTL_I_DCI
D2
HSTL_I_DCI
F3
HSTL_I_DCI
G2
HSTL_I_DCI
J3
HSTL_I_DCI
L3
HSTL_I_DCI
M3
HSTL_I_DCI
N2
HSTL_I_DCI
A3
HSTL_I_DCI
A9
HSTL_I_DCI
B4
termination voltage
TT
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
A0
A1
A2
16
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