Xilinx VCU110 User Manual page 142

Hide thumbs Also See for VCU110:
Table of Contents

Advertisement

set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
# HMC
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
PACKAGE_PIN H23
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_DK0_P"]
PACKAGE_PIN G22
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_DK1_N"]
PACKAGE_PIN H22
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_DK1_P"]
PACKAGE_PIN D27
IOSTANDARD
SSTL12
PACKAGE_PIN D26
IOSTANDARD
SSTL12
PACKAGE_PIN M28
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK1_N"]
PACKAGE_PIN N28
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK1_P"]
PACKAGE_PIN H29
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK2_N"]
PACKAGE_PIN H28
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK2_P"]
PACKAGE_PIN L31
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK3_N"]
PACKAGE_PIN M31
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_QK3_P"]
PACKAGE_PIN A26
IOSTANDARD
SSTL12
PACKAGE_PIN G27
IOSTANDARD
SSTL12
PACKAGE_PIN F25
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_CK_N"]
PACKAGE_PIN G25
IOSTANDARD
DIFF_SSTL12 [get_ports "RLD3_36B_CK_P"]
PACKAGE_PIN A25
IOSTANDARD
SSTL12
PACKAGE_PIN A24
IOSTANDARD
SSTL12
PACKAGE_PIN F21
IOSTANDARD
SSTL12
PACKAGE_PIN E22
IOSTANDARD
SSTL12
PACKAGE_PIN AW27
IOSTANDARD
LVCMOS15
PACKAGE_PIN AY29
IOSTANDARD
LVCMOS15
PACKAGE_PIN AY30
IOSTANDARD
LVCMOS15
PACKAGE_PIN BB27
IOSTANDARD
LVCMOS15
PACKAGE_PIN BA26
IOSTANDARD
LVCMOS15
PACKAGE_PIN BB26
IOSTANDARD
LVCMOS15
PACKAGE_PIN AV30
IOSTANDARD
LVCMOS15
PACKAGE_PIN AW30
IOSTANDARD
LVCMOS15
PACKAGE_PIN AW28
IOSTANDARD
LVCMOS15
www.xilinx.com
Appendix D:
Master Constraints File Listing
[get_ports "RLD3_36B_DK0_P"]
[get_ports "RLD3_36B_DK1_N"]
[get_ports "RLD3_36B_DK1_P"]
[get_ports "RLD3_36B_QK0_N"]
[get_ports "RLD3_36B_QK0_N"]
[get_ports "RLD3_36B_QK0_P"]
[get_ports "RLD3_36B_QK0_P"]
[get_ports "RLD3_36B_QK1_N"]
[get_ports "RLD3_36B_QK1_P"]
[get_ports "RLD3_36B_QK2_N"]
[get_ports "RLD3_36B_QK2_P"]
[get_ports "RLD3_36B_QK3_N"]
[get_ports "RLD3_36B_QK3_P"]
[get_ports "RLD3_36B_QVLD0"]
[get_ports "RLD3_36B_QVLD0"]
[get_ports "RLD3_36B_QVLD1"]
[get_ports "RLD3_36B_QVLD1"]
[get_ports "RLD3_36B_CK_N"]
[get_ports "RLD3_36B_CK_P"]
[get_ports "RLD3_36B_WE_B"]
[get_ports "RLD3_36B_WE_B"]
[get_ports "RLD3_36B_REF_B"]
[get_ports "RLD3_36B_REF_B"]
[get_ports "RLD3_36B_RESET_B"]
[get_ports "RLD3_36B_RESET_B"]
[get_ports "RLD3_36B_CS_B"]
[get_ports "RLD3_36B_CS_B"]
[get_ports "HMC_L0TXPS"]
[get_ports "HMC_L0TXPS"]
[get_ports "HMC_L1TXPS"]
[get_ports "HMC_L1TXPS"]
[get_ports "HMC_L0RXPS"]
[get_ports "HMC_L0RXPS"]
[get_ports "HMC_L1RXPS"]
[get_ports "HMC_L1RXPS"]
[get_ports "HMC_REFCLK_BOOT_0"]
[get_ports "HMC_REFCLK_BOOT_0"]
[get_ports "HMC_REFCLK_BOOT_1"]
[get_ports "HMC_REFCLK_BOOT_1"]
[get_ports "HMC_REFCLK_SEL"]
[get_ports "HMC_REFCLK_SEL"]
[get_ports "HMC_FERR_B"]
[get_ports "HMC_FERR_B"]
[get_ports "HMC_P_RST_B"]
[get_ports "HMC_P_RST_B"]
142
Send Feedback

Advertisement

Table of Contents
loading

Table of Contents