Xilinx VCU110 User Manual page 55

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Table 1-20: VCU110 FPGA U1 GTY Quad 128 Connections
FPGA (U1) Pin Name
MGTYTXP0_128
MGTYTXN0_128
MGTYRXP0_128
MGTYRXN0_128
MGTYTXP1_128
MGTYTXN1_128
MGTYRXP1_128
MGTYRXN1_128
MGTYTXP2_128
MGTYTXN2_128
MGTYRXP2_128
MGTYRXN2_128
MGTYTXP3_128
MGTYTXN3_128
MGTYRXP3_128
MGTYRXN3_128
MGTREFCLK0P_128
MGTREFCLK0N_128
MGTREFCLK1P_128
MGTREFCLK1N_128
Notes:
1. MGT connections I/O standard not applicable
2. Series capacitor coupled
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
(U1) Pin
W40
CFP4_MOD3_TX3_P
W41
CFP4_MOD3_TX3_N
W45
CFP4_MOD3_RX3_P
W46
CFP4_MOD3_RX3_N
V38
CFP4_MOD3_TX2_P
V39
CFP4_MOD3_TX2_N
V43
CFP4_MOD3_RX2_P
V44
CFP4_MOD3_RX2_N
U40
CFP4_MOD3_TX1_P
U41
CFP4_MOD3_TX1_N
U45
CFP4_MOD3_RX1_P
U46
CFP4_MOD3_RX1_N
T38
CFP4_MOD3_TX0_P
T39
CFP4_MOD3_TX0_N
T43
CFP4_MOD3_RX0_P
T44
CFP4_MOD3_RX0_N
W36
CFP4_SI5328_OUT1_BUF4_C_P
W37
CFP4_SI5328_OUT1_BUF4_C_N
V34
CFP4_REC_CLOCK2_C_P(1)
V35
CFP4_REC_CLOCK2_C_N(1)
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected
(1)
Pin Number
Pin Name
54
TX3P--TX0P
55
TX3N--TX0N
39
RX3P--RX3N
40
RX3N--RX3P
51
TX2P--TX1P
52
TX2N--TX1N
36
RX2P--RX2N
37
RX2N--RX2P
48
TX1P--TX2P
49
TX1N--TX2N
33
RX1P--RX1N
34
RX1N--RX1P
45
TX0P--TX3P
46
TX0N--TX3N
30
RX0N--RX0P
31
RX0P--RX0N
(2)
28
CKOUT1_P
(2)
29
CKOUT1_N
12
CKIN2_P
13
CKIN2_N
Send Feedback
Connected
Device
CFP4
MOD3
J110
SI5328
U179
SI5328
U179
55

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