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Table 1-33: VCU110 FPGA U1 GTH Quad 228 Connections
FPGA (U1)
FPGA (U1) Pin Name
MGTHTXP0_228
MGTHTXN0_228
MGTHRXP0_228
MGTHRXN0_228
MGTHTXP1_228
MGTHTXN1_228
MGTHRXP1_228
MGTHRXN1_228
MGTHTXP2_228
MGTHTXN2_228
MGTHRXP2_228
MGTHRXN2_228
MGTHTXP3_228
MGTHTXN3_228
MGTHRXP3_228
MGTHRXN3_228
MGTREFCLK0P_228
MGTREFCLK0N_228
MGTREFCLK1P_228
MGTREFCLK1N_228
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net Name
Pin
W7
HMC_L1TX_12_P
W6
HMC_L1TX_12_N
W2
HMC_L1RX_12_C_P
W1
HMC_L1RX_12_C_N
V9
HMC_L1TX_10_P
V8
HMC_L1TX_10_N
V4
HMC_L1RX_10_C_P
V3
HMC_L1RX_10_C_N
U7
HMC_L1TX_9_P
U6
HMC_L1TX_9_N
U2
HMC_L1RX_9_C_P
U1
HMC_L1RX_9_C_N
T9
HMC_L1TX_8_P
T8
HMC_L1TX_8_N
T4
HMC_L1RX_8_C_P
T3
HMC_L1RX_8_C_N
W11
NA
W10
NA
V13
NA
V12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
Connected Pin
(1)
Pin Number
AC25
L1RXP_12
AC24
L1RXN_12
(2)
AB28
L1TXP_12
(2)
AB27
L1TXN_12
AH30
L1RXP_10
AH29
L1RXN_10
(2)
AD22
L1TXP_10
(2)
AD21
L1TXN_10
W28
L1RXP_9
W27
L1RXN_9
(2)
Y26
L1TXP_9
(2)
Y25
L1TXN_9
Y30
L1RXP_8
Y29
L1RXN_8
(2)
AA27
L1TXP_8
(2)
AA26
L1TXN_8
NA
NA
NA
NA
Connected
Name
Device
HMC
U160
NA
NA
NA
NA
NA
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