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Table 1-8: HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232 (Cont'd)
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_231
MGTHTXN0_231
MGTHRXP0_231
MGTHRXN0_231
MGTHTXP1_231
MGTHTXN1_231
MGTHRXP1_231
MGTHRXN1_231
MGTHTXP2_231
GTH
MGTHTXN2_231
Quad
MGTHRXP2_231
231
MGTHRXN2_231
MGTHTXP3_231
MGTHTXN3_231
MGTHRXP3_231
MGTHRXN3_231
MGTREFCLK0P_231
MGTREFCLK0N_231
MGTREFCLK1P_231
MGTREFCLK1N_231
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
(U1)
Schematic Net Name
Pin
G7
HMC_L0TX_4_P
G6
HMC_L0TX_4_N
G2
HMC_L0RX_4_C_P
G1
HMC_L0RX_4_C_N
F9
HMC_L0TX_11_P
F8
HMC_L0TX_11_N
F4
HMC_L0RX_11_C_P
F3
HMC_L0RX_11_C_N
G11
HMC_L0TX_6_P
G10
HMC_L0TX_6_N
G16
HMC_L0RX_6_C_P
G15
HMC_L0RX_6_C_N
F13
HMC_L0TX_2_P
F12
HMC_L0TX_2_N
E16
HMC_L0RX_2_C_P
E15
HMC_L0RX_2_C_N
N11
NA
N10
NA
M13
NA
M12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
L30
L29
K27
K26
M28
M27
L26
L25
C30
C29
G22
G21
D29
D28
C26
C25
NA
NA
NA
NA
Send Feedback
Connected Pin
Connected
Name
Device
L0RXP_8
L0RXN_8
L0TXP_8
L0TXN_8
L0RXP_9
L0RXN_9
L0TXP_9
L0TXN_9
HMC
U160
L0RXP_10
L0RXN_10
L0TXP_10
L0TXN_10
L0RXP_11
L0RXN_11
L0TXP_11
L0TXN_11
NA
NA
NA
NA
NA
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