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SYSMON Headers J80, J81
UltraScale FPGAs provide an analog front end (SYSMON) block. The SYSMON contains a
single 10-bit 0.2 MSPS ADC. Consequently, the sequencer for SYSMON does not support
simultaneous sampling mode or independent ADC mode. See the UltraScale architecture
System Monitor (SYSMON) User Guide (UG580)
analog front end.
The VCU110 board supports both the internal FPGA sensor measurements and the external
measurement capabilities of the SYSMON. Internal measurements of the die temperature,
V
, V
, and V
CCINT
CCAUX
The FPGA U1 Bank 0 dedicated VP (FPGA U1 pin AC20) and VN (FPGA U1 pin AD19) input
channel pins are dual-purpose. When pulled to GND through 20.5 kΩ resistors, the default
SYSMON I2C address is set pre-configuration. The VCU110 implements 2-pin male headers
(J80, J81) which can be jumpered to these pull-down resistors. The headers can be used as
dedicated analog inputs post-configuration by removing the jumpers.
For external measurements, SYSMON headers (J80, J81) are provided to connect analog
inputs to the FPGA VP and VN input pins. See pages 54/55 of UG580
For more detailed information about the UltraScale System Monitor (SYSMON), see
UltraScale Architecture System Monitor User Guide, (UG580)
Cooling Fan
The XCVU190 FPGA U1 cooling fan connector is shown in
The fan turns on when the VCU110 is powered on due to pull-up resistor R422. The
SM_FAN_PWM and SM_FAN_TACH signals are wired to XCVU190 FPGA U1 Bank 65 pins
AT21 and AT19 respectively, enabling the user to implement their own fan speed control IP
in the FPGA U1 logic.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
are available.
CCBRAM
www.xilinx.com
Chapter 1:
VCU110 Evaluation Board Features
[Ref 15]
for details on the capabilities of the
[Ref
15].
Figure
1-31.
[Ref 15]
for details.
126
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