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Table 1-8: HMC Memory U160 L0 I/F to FPGA U1 GTH Quads 229-232 (Cont'd)
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_230
MGTHTXN0_230
MGTHRXP0_230
MGTHRXN0_230
MGTHTXP1_230
MGTHTXN1_230
MGTHRXP1_230
MGTHRXN1_230
MGTHTXP2_230
GTH
MGTHTXN2_230
Quad
MGTHRXP2_230
230
MGTHRXN2_230
MGTHTXP3_230
MGTHTXN3_230
MGTHRXP3_230
MGTHRXN3_230
MGTREFCLK0P_230
MGTREFCLK0N_230
MGTREFCLK1P_230
MGTREFCLK1N_230
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
(U1)
Schematic Net Name
Pin
L7
HMC_L0TX_10_P
L6
HMC_L0TX_10_N
L2
HMC_L0RX_10_C_P
L1
HMC_L0RX_10_C_N
K9
HMC_L0TX_14_P
K8
HMC_L0TX_14_N
K4
HMC_L0RX_14_C_P
K3
HMC_L0RX_14_C_N
J7
HMC_L0TX_0_P
J6
HMC_L0TX_0_N
J2
HMC_L0RX_0_C_P
J1
HMC_L0RX_0_C_N
H9
HMC_L0TX_1_P
H8
HMC_L0TX_1_N
H4
HMC_L0RX_1_C_P
H3
HMC_L0RX_1_C_N
R11
HMC_SI5328_OUT2_BUF1_C_P
R10
HMC_SI5328_OUT2_BUF1_C_N
P13
NA
P12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
E20
E19
D25
D24
D21
D20
B27
B26
C22
C21
A20
A19
B23
B22
B19
B18
35
34
NA
NA
Send Feedback
Connected Pin
Connected
Name
Device
L0RXP_4
L0RXN_4
L0TXP_4
L0TXN_4
L0RXP_5
L0RXN_5
L0TXP_5
L0TXN_5
HMC
U160
L0RXP_6
L0RXN_6
L0TXP_6
L0TXN_6
L0RXP_7
L0RXN_7
L0TXP_7
L0TXN_7
CKOUT2_P
SI5328
U57
CKOUT2_N
NA
NA
NA
27
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