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Table 1-9: HMC Memory U160 L1 I/F to FPGA U1 GTH Quads 225-228 (Cont'd)
MGT
FPGA (U1) Pin Name
Bank
MGTHTXP0_228
MGTHTXN0_228
MGTHRXP0_228
MGTHRXN0_228
MGTHTXP1_228
MGTHTXN1_228
MGTHRXP1_228
MGTHRXN1_228
MGTHTXP2_228
GTH
MGTHTXN2_228
Quad
MGTHRXP2_228
228
MGTHRXN2_228
MGTHTXP3_228
MGTHTXN3_228
MGTHRXP3_228
MGTHRXN3_228
MGTREFCLK0P_228
MGTREFCLK0N_228
MGTREFCLK1P_228
MGTREFCLK1N_228
Notes:
1. MGT connections I/O standard not applicable.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
(U1)
Schematic Net Name
Pin
W7
HMC_L1TX_12_P
W6
HMC_L1TX_12_N
W2
HMC_L1RX_12_C_P
W1
HMC_L1RX_12_C_N
V9
HMC_L1TX_10_P
V8
HMC_L1TX_10_N
V4
HMC_L1RX_10_C_P
V3
HMC_L1RX_10_C_N
U7
HMC_L1TX_9_P
U6
HMC_L1TX_9_N
U2
HMC_L1RX_9_C_P
U1
HMC_L1RX_9_C_N
T9
HMC_L1TX_8_P
T8
HMC_L1TX_8_N
T4
HMC_L1RX_8_C_P
T3
HMC_L1RX_8_C_N
W11
NA
W10
NA
V13
NA
V12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
AK24
AK23
AH18
AH17
AK16
AK15
AG17
AG16
AE19
AE18
AE23
AE22
AD18
AD17
AF24
AF23
NA
NA
NA
NA
Send Feedback
Connected
Connected
Pin Name
Device
L1RXP_3
L1RXN_3
L1TXP_3
L1TXN_3
L1RXP_2
L1RXN_2
L1TXP_2
L1TXN_2
HMC
U160
L1RXP_1
L1RXN_1
L1TXP_1
L1TXN_1
L1RXP_0
L1RXN_0
L1TXP_0
L1TXN_0
NA
NA
NA
NA
NA
33
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