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Table 1-22: VCU110 FPGA U1 GTY Quad 130 Connections
FPGA (U1) Pin Name
(U1) Pin
MGTYTXP0_130
MGTYTXN0_130
MGTYRXP0_130
MGTYRXN0_130
MGTYTXP1_130
MGTYTXN1_130
MGTYRXP1_130
MGTYRXN1_130
MGTYTXP2_130
MGTYTXN2_130
MGTYRXP2_130
MGTYRXN2_130
MGTYTXP3_130
MGTYTXN3_130
MGTYRXP3_130
MGTYRXN3_130
MGTREFCLK0P_130
MGTREFCLK0N_130
MGTREFCLK1P_130
MGTREFCLK1N_130
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
FPGA
Schematic Net Name
L40
ILKN_TX4_P
L41
ILKN_TX4_N
L45
ILKN_RX4_C_P
L46
ILKN_RX4_C_N
K38
ILKN_TX5_P
K39
ILKN_TX5_N
K43
ILKN_RX5_C_P
K44
ILKN_RX5_C_N
J40
ILKN_TX6_P
J41
ILKN_TX6_N
J45
ILKN_RX6_C_P
J46
ILKN_RX6_C_N
H38
ILKN_TX7_P
H39
ILKN_TX7_N
H43
ILKN_RX7_C_P
H44
ILKN_RX7_C_N
R36
ILKN_SI5328_OUT2_BUF2_C_P
R37
ILKN_SI5328_OUT2_BUF2_C_N
P34
NA
P35
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected
(1)
Pin Number
A8
A9
(2)
B8
(2)
B9
C8
C9
(2)
D8
(2)
D9
F2
F3
(2)
G2
(2)
G3
H2
H3
(2)
J2
(2)
J3
(2)
35
(2)
34
NA
NA
Connected
Connected
Pin Name
Device
TX4_P
TX4_N
RX4_P
RX4_N
TX5_P
TX5_N
RX5_P
RX5_N
Interlaken
J121
TX6_P
TX6_N
RX6_P
RX6_N
TX7_P
TX7_N
RX7_P
RX7_N
CKOUT2_P
SI5328
U181
CKOUT2_N
NA
NA
NA
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