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Table 1-30: VCU110 FPGA U1 GTH Quad 225 Connections
FPGA (U1)
FPGA (U1) Pin Name
MGTHTXP0_225
MGTHTXN0_225
MGTHRXP0_225
MGTHRXN0_225
MGTHTXP1_225
MGTHTXN1_225
MGTHRXP1_225
MGTHRXN1_225
MGTHTXP2_225
MGTHTXN2_225
MGTHRXP2_225
MGTHRXN2_225
MGTHTXP3_225
MGTHTXN3_225
MGTHRXP3_225
MGTHRXN3_225
MGTREFCLK0P_225
MGTREFCLK0N_225
MGTREFCLK1P_225
MGTREFCLK1N_225
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
Schematic Net
(1)
Pin
Name
AL7
HMC_L1TX_0_P
AL6
HMC_L1TX_0_N
AL2
HMC_L1RX_0_C_P
AL1
HMC_L1RX_0_C_N
AK9
HMC_L1TX_2_P
AK8
HMC_L1TX_2_N
AK4
HMC_L1RX_2_C_P
AK3
HMC_L1RX_2_C_N
AJ7
HMC_L1TX_1_P
AJ6
HMC_L1TX_1_N
AJ2
HMC_L1RX_1_C_P
AJ1
HMC_L1RX_1_C_N
AH9
HMC_L1TX_6_P
AH8
HMC_L1TX_6_N
AH4
HMC_L1RX_6_C_P
AH3
HMC_L1RX_6_C_N
AE11
NA
AE10
NA
AD13
NA
AD12
NA
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Chapter 1:
VCU110 Evaluation Board Features
Connected Pin
Connected Pin
Number
AD18
AD17
(2)
AF24
(2)
AF23
AK16
AK15
(2)
AG17
(2)
AG16
AE19
AE18
(2)
AE23
(2)
AE22
AH22
AH21
(2)
AK20
(2)
AK19
NA
NA
NA
NA
Connected
Name
Device
L1RXP_0
L1RXN_0
L1TXP_0
L1TXN_0
L1RXP_2
L1RXN_2
L1TXP_2
L1TXN_2
HMC
U160
L1RXP_1
L1RXN_1
L1TXP_1
L1TXN_1
L1RXP_6
L1RXN_6
L1TXP_6
L1TXN_6
NA
NA
NA
NA
NA
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