User Clock Source; User Sma Clock Input - Xilinx KC705 User Manual

The user clock circuit is shown in
X-Ref Target - Figure 1-11
To I 2 C
Bus Switch
(U49)
For more information about the Silicon Labs Si570 see
Reference design files are available to demonstrate how to program the Si570
programmable oscillator. See these files and presentations:
• XTP186, KC705 Si570 Programming
• RDF0175, KC705 Si570 Programming Design Files
• XTP187, KC705 Si570 Fixed Frequencies
• RDF0176, KC705 Si570 Fixed Frequencies Design Files

User SMA Clock Input

[Figure 1-2, callout 9]
An external high-precision clock signal can be provided to the FPGA bank 15 by connecting
differential clock signals through the onboard 50Ω SMA connectors J11 (P) and J12 (N). The
differential clock has signal names are USER_SMA_CLOCK_P and USER_SMA_CLOCK_N,
which are connected to FPGA U1 pins L25 and K25, respectively. J11 (P) and J12 (N) are
connected directly to the noted FPGA pins (no series capacitors and no external parallel
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Figure 1-11.
VCC3V3
R8
4.7KΩ 5%
U45
Si570
Programmable
Oscillator
1
NC
2
OE
7
USER CLOCK SDA
SDA
8
USER CLOCK SCL
SCL
3
GND
GND
Figure 1-11: User Clock Source
[Ref 8]
[Ref 10]
www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
VCC3V3
C77
0.01 μF 25V
X7R
GND
6
VDD
5 USER CLOCK N
CLK-
4 USER CLOCK P
CLK+
[Ref 7].
[Ref 9]
[Ref 11]
10 MHz - 810 MHz
50 PPM
UG810_c1_11_031214
30
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