System Clock; Programmable User Clock - Xilinx ZC702 User Manual

Table 1-12: Clock Connections, Source to XC7Z020 AP SoC
Clock Source Pin
U28.4
J65.3

System Clock

[Figure 1-2, callout 7]
The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region
clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named
SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively
on the XC7Z020 AP SoC.
• Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
• Frequency jitter: 50 ppm
• Differential Output
For more details, see the SiTime SiT9102 data sheet
shown in Figure
X-Ref Target - Figure 1-11
C71
0.1 µF 10V
X5R

Programmable User Clock

[Figure 1-2, callout 8]
The ZC702 board has a programmable low-jitter 3.3V LVDS differential oscillator (U28)
connected to the MRCC inputs of bank 13. This USRCLK_P and USRCLK_N clock signal pair
is connected to XC7Z020 AP SoC U1 pins Y9 and Y8 respectively. On power-up the user
clock defaults to an output frequency of 156.250 MHz. User applications can change the
output frequency within the range of 10 MHz to 810 MHz through an I
cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz.
• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Net Name XC7Z020 (U1) Pin
USRCLK_P
PS_CLK
1-11.
U43
SIT9102
200 MHz
Oscillator
1
OE VCC
2
NC OUT_B
3
GND OUT
GND
Figure 1-11: System Clock Source
www.xilinx.com
Y9
F7 (Bank 500)
[Ref 5]. The system clock circuit is
VCC2V5
6
R168
5
100Ω 1%
4
Feature Descriptions
SYSCLK_N
SYSCLK_P
UG850_c1_11_030513
2
C interface. Power
28