Programmable User Clock; Processing System Clock Source - Xilinx ZC702 User Manual

Programmable User Clock

[Figure 1-2, callout 8]
The ZC702 board has a programmable low-jitter 3.3V LVDS differential oscillator (U28)
connected to the MRCC inputs of bank 13. This USRCLK_P and USRCLK_N clock signal pair
is connected to XC7Z020 AP SoC U1 pins Y9 and Y8 respectively. On power-up the user
clock defaults to an output frequency of 156.250 MHz. User applications can change the
output frequency within the range of 10 MHz to 810 MHz through an I
cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz.
• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)
• LVDS Differential Output
The user clock circuit is shown in
X-Ref Target - Figure 1-12
VCC3V3
USRCLK SDA
USR CLK SCL
The Silicon Labs Si570 data sheet is available on the Silicon Labs website

Processing System Clock Source

[Figure 1-2, callout 8]
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed
33.33333 MHz oscillator at U65. It is wired to PS bank 500, pin F7 (PS_CLK), on the XC7Z020
AP SoC.
• Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz)
• Frequency jitter: 50 ppm
• Single-ended output
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
Figure
U28
R20
Si570
4.7KΩ 5%
Programmable
Oscillator
1
NC VDD
2
OE
7
SDA
CLK-
8
SCL CLK+
3
GND
GND
Figure 1-12: User Clock Source
www.xilinx.com
1-12.
VCC3V3
C216
0.01 μF 25V
X7R
6
GND
USRCLK N
R417
5
100Ω 1%
4 USRCLK P
UG850_c1_12_030513
Feature Descriptions
2
C interface. Power
[Ref 20].
29
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