Programmable User Si570 Clocks - Xilinx Zynq UltraScale+ ZCU216 User Manual

• Outputs:
OUT0: 27 MHz
○
Enabled, LVDS 3.3 V
○
OUT1: Unused
○
OUT2: 26 MHz
○
Enabled, LVDS 3.3 V
○
OUT3: 125 MHz
○
Enabled, LVDS 3.3 V
○
OUT4: 100 MHz
○
Enabled, HCSL 3.3 V
○
OUT5: 100 MHz
○
Enabled, LVDS 3.3 V
○
OUT6: 125 MHz
○
Enabled, LVDS 3.3 V
○
OUT7: 74.25 MHz [ 74 + 1/4 MHz ]
○
Enabled, LVDS 3.3 V
○
OUT8: Unused
○
OUT9: 33.3333333333333333... MHz [ 33 + 1/3 MHz ]
○
Enabled, LVCMOS In-Phase 1.8V
○

Programmable User SI570 Clocks

[Figure 2, callouts 11 and 12]
The ZCU216 board has three I2C programmable SI570 low-jitter 3.3V LVDS differential
oscillators, two assigned to the DDR4 component memory interface banks (Bank 65 I/F C0: U47
and Bank 69 I/F C1: U130) and one assigned to GTY131 (U48).
On power-up the user clocks default to a pre-programmed output frequency: DDR4 I/F U47 and
U130 to 300.000 MHz and GTY I/F U48 to 156.250 MHz.
User applications can change the output frequency of each SI570 within the range of 10 MHz to
810 MHz through the I2C1 bus interface. Power cycling the ZCU216 board reverts user clocks to
their default settings.
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Chapter 3: Board Component Descriptions
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