System Clock - Xilinx KCU116 User Manual

Table 3-6 lists the FPGA connections for each clock.
Table 3‐6: KCU116 Clock Sources to XCKU5P FPGA U1 Connections
Clock Source
Ref.Des. and Pin
U170.22
U170.21
U170.18
U170.17
U170.14
U170.10
U56.4
U56.5
J168.1
J169.1
U20.28
U20.29
U179.4
U179.5
Notes:
1. AC capacitively coupled, MGT connections I/O standard not applicable.
2. Series resistor terminated.

System Clock

[Figure 2-1, callout 6]
The system clock source is a Silicon Labs SI5335A quad clock generator/buffer (U170). The
system clock (SYSCLK) is a LVDS 300 MHz clock sourced from the CLK0A output pair of
U170. SYSCLK is wired to a clock capable (GC) input on programmable logic bank 66. The
signal pair named SYSCLK_300_P and SYSCLK_300_N are connected to XCKU5P FPGA U1
(bank 66 pins K22 and K23, respectively).
• Clock generator: Silicon Labs SI5335A-B03426-GM (CLK0A 300 MHz)
• Low phase jitter of 0.7 pS RMS
• LVDS differential output
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Schematic Net Name
(1)
SYSCLK_300_P
(1)
SYSCLK_300_N
CLK_125MHZ_P
CLK_125MHZ_N
(2)
FPGA_EMCCLK
(2)
SYSCTLR_CLK
USER_MGT_SI570_CLOCK_P
USER_MGT_SI570_CLOCK_N
USER_SMA_CLOCK_P
USER_SMA_CLOCK_N
(1)
SFP_SI5328_OUT_P
(1)
SFP_SI5328_OUT_N
CLK_74_25_P
CLK_74_25_N
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Chapter 3: Board Component Descriptions
I/O Standard
LVDS
LVDS
LVDS
LVDS
LVCMOS18
LVCMOS18
(1)
LVDS
(1)
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
XCKU5P FPGA
(U1) Pin
K22
K23
G12
F12
N21
U161.C7
M7
M6
J23
J24
P7
P6
D11
D10
29
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