System Clock - Xilinx ZC706 User Manual

Table 1-12: ZC706 Evaluation Board Clock Sources
Clock Name

System Clock

User Clock
User SMA Clock
PS Clock
GTX SMA REF Clock
Jitter Attenuated Clock
Table 1-13 lists the pin-to-pin connections from each clock source to the XC7Z045 AP SoC.
Table 1-13: Clock Connections, Source to XC7Z045 AP SoC
Clock Source Pin
U64.5
U64.4
U37.5
U37.4
J67.1
J68.1
J24.3
J36.1
J31.1
U60.29
U60.28
U60.17
U60.16
U60.3
U60.1
Notes:
1. PS-side and GTX nets do not have an assigned I/O standard.
System Clock
[Figure 1-2, callout 7]
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Clock Source
SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime).
U64
See System Clock, page
Si570 3.3V LVDS I
U37
(Silicon Labs). See
User clock input SMAs, limit input swing voltage to VADJ_FPGA setting
J67(P), J68(N)
(1.8V, 2.5V, 3.3V). See
SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency
U24
oscillator (SiTime). See
User clock input SMAs. See
J36(P), J31(N)
SMA_MGT_REFCLK_N), page
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).
U60
See Jitter Attenuated Clock, page
Net Name
SYSCLK_N
SYSCLK_P
USRCLK_N
USRCLK_P
USER_SMA_CLOCK_P
USER_SMA_CLOCK_N
PS_CLK
SMA_MGT_REFCLK_P
SMA_MGT_REFCLK_N
SI5324_OUT_C_N
SI5324_OUT_C_P
REC_CLOCK_C_N
REC_CLOCK_C_P
SI5324_INT_ALM_LS
SI5324_RST_LS
www.xilinx.com
Description
34.
2
C programmable oscillator, 156.250 MHz default
Programmable User Clock, page
User SMA Clock Source, page
Processing System Clock Source, page
GTX SMA Clock (SMA_MGT_REFCLK_P and
37.
38.
I/O Standard XC7Z045 (U1) Pin
LVDS G9
LVDS H9
LVDS_25 AG14
LVDS_25 AF14
LVDS_25 AD18
LVDS_25 AD19
NA(1) A22 (Bank 500)
NA(1) W8
NA(1) W7
NA(1) AC7
NA(1) AC8
LVDS_25 AE20
LVDS_25 AD20
LVCMOS25 AJ25
LVCMOS25 W23
Feature Descriptions
35.
36.
37.
34
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